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參數(shù)資料
| 型號： | NAND01GR3A2AZA6E |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 128M X 8 FLASH 1.8V PROM, 15000 ns, PBGA63 |
| 封裝： | 8.50 X 15 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, TFBGA-63 |
| 文件頁數(shù)： | 7/56頁 |
| 文件大?。?/td> | 871K |
| 代理商： | NAND01GR3A2AZA6E |
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A
MEMORY ARRAY ORGANIZATION
The memory array is made up of NAND structures
where 16 cells are connected in series.
The memory array is organized in blocks where
each block contains 32 pages. The array is split
into two areas, the main area and the spare area.
The main area of the array is used to store data
whereas the spare area is typically used to store
Error correction Codes, software flags or Bad
Block identification.
In x8 devices the pages are split into a main area
with two half pages of 256 Bytes each and a spare
area of 16 Bytes. In the x16 devices the pages are
split into a 256 Word main area and an 8 Word
spare area. Refer to Figure 10., Memory Array Or-
Bad Blocks
The NAND Flash 528 Byte/ 264 Word Page devic-
es may contain Bad Blocks, that is blocks that con-
tain one or more invalid bits whose reliability is not
guaranteed. Additional Bad Blocks may develop
during the lifetime of the device.
The Bad Block Information is written prior to ship-
ping (refer to Bad Block Management section for
more details).
Table 4. shows the minimum number of valid
blocks in each device. The values shown include
both the Bad Blocks that are present when the de-
vice is shipped and the Bad Blocks that could de-
velop later on.
These blocks need to be managed using Bad
Blocks Management, Block Replacement or Error
Correction Codes (refer to SOFTWARE ALGO-
RITHMS section).
Table 4. Valid Blocks
Figure 10. Memory Array Organization
Density of Device
Min
Max
1Gbit
8032
8192
512Mbits
4016
4096
256Mbits
2008
2048
128Mbits
1004
1024
AI07587
Block = 32 Pages
Page = 528 Bytes (512+16)
512 Bytes
Sp
are
Are
a
2nd half Page
(256 bytes)
16
Bytes
Block
8 bits
16
Bytes
8 bits
Page
Page Buffer, 512 Bytes
1st half Page
(256 bytes)
Block = 32 Pages
Page = 264 Words (256+8)
256 Words
Sp
are
Are
a
Main Area
8
Words
16 bits
8
Words
16 bits
Page Buffer, 264 Words
Block
Page
x8 DEVICES
x16 DEVICES
相關PDF資料 |
PDF描述 |
|---|---|
| NAND01GR3A2AZA6 | 128M X 8 FLASH 1.8V PROM, 15000 ns, PBGA63 |
| NAND01GR4B2BZA1F | 64M X 16 FLASH 1.8V PROM, 25000 ns, PBGA63 |
| NAND08GR4B3AZB6 | 512M X 16 FLASH 1.8V PROM, 25000 ns, PBGA63 |
| NAND256W4A2AZA6E | 16M X 16 FLASH 3V PROM, 12000 ns, PBGA55 |
| NCP303LSN41T1 | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5 |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NAND01GR3A2AZA6F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories |
| NAND01GR3A2AZA6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories |
| NAND01GR3A2AZB1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories |
| NAND01GR3A2AZB1E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories |
| NAND01GR3A2AZB1F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories |
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