參數(shù)資料
型號: MXB7846EUE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: 2.375V to 5.25V, 4-Wire Touch-Screen Controller with Internal Reference and Temperature Sensor
中文描述: 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16
封裝: 4.40 MM, 0.65 MM PITCH, MO-153AC, TSSOP-16
文件頁數(shù): 15/23頁
文件大?。?/td> 967K
代理商: MXB7846EUE
M
2.375V to 5.25V, 4-Wire Touch-Screen Controller
with Internal Reference and Temperature Sensor
______________________________________________________________________________________
15
Start a conversion by clocking a control byte into DIN
(Table 3) with
CS
low. Each rising edge on DCLK
clocks a bit from DIN into the MXB7846’s internal shift
register. After
CS
falls, the first arriving logic 1 bit
defines the control byte’s START bit. Until the START bit
arrives, any number of logic 0 bits can be clocked into
DIN with no effect.
The MXB7846 is compatible with SPI/QSPI/MICROWIRE
devices. For SPI, select the correct clock polarity and
sampling edge in the SPI control registers of the micro-
controller: set CPOL = 0 and CPHA = 0. MICROWIRE,
SPI, and QSPI all transmit a byte and receive a byte at
the same time. The simplest software interface requires
only three 8-bit transfers to perform a conversion (one 8-
bit transfer to configure the ADC, and two more 8-bit
transfers to read the conversion result; Figure 9).
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 500kHz to 2MHz:
1) Set up the control byte and call it TB. TB should be
in the format: 1XXXXXXX binary, where X denotes
the particular channel, selected conversion mode,
and power mode (Tables 3, 4).
2) Use a general-purpose I/O line on the CPU to pull
CS
low.
3) Transmit TB and simultaneously receive a byte; call
it RB1.
4) Transmit a byte of all zeros ($00 hex) and simultane-
ously receive byte RB2.
5) Transmit a byte of all zeros ($00 hex) and simultane-
ously receive byte RB3.
6) Pull
CS
high.
Figure 9 shows the timing for this sequence. Byte RB2
and RB3 contain the result of the conversion, padded
with four trailing zeros. The total conversion time is a
function of the serial-clock frequency and the amount of
idle timing between 8-bit transfers.
Digital Output
The MXB7846 outputs data in straight binary format. Data
is clocked out on the falling edge of the DCLK MSB first.
Serial Clock
The external clock not only shifts data in and out, but it
also drives the analog-to-digital conversion steps.
BUSY pulses high for one clock period after the last bit
of the control byte. Successive-approximation bit deci-
sions are made and appear at DOUT on each of the
next 12 DCLK falling edges. BUSY and DOUT go into a
high-impedance state when
CS
goes high.
The conversion must complete in 500μs or less; if not,
droop on the sample-and-hold capacitors can degrade
conversion results.
Data Framing
The falling edge of
CS
does not start a conversion. The
first logic high clocked into DIN is interpreted as a start
bit and defines the first bit of the control byte. A conver-
sion starts on DCLK’s falling edge, after the eighth bit of
the control byte is clocked into DIN.
The first logic 1 clocked into DIN after bit 6 of a conver-
sion in progress is clocked onto the DOUT pin and is
treated as a START bit (Figure 10).
Once a start bit has been recognized, the current con-
version must be completed.
BIT 7
START
BIT 6
A2
BIT 5
A1
BIT 4
A0
BIT 3
MODE
BIT 2
SER/
DFR
BIT 1
PD1
BIT 0
PD0
BIT
7
6
5
4
3
2
1
0
NAME
START
A2
A1
A0
MODE
SER/
DFR
PD1
PD0
DESCRIPTION
Start bit
Address (Tables 1 and 2)
Conversion resolution: 1 = 8 bits, 0 = 12 bits
Conversion mode: 1 = single ended, 0 = differential
Power-down mode (Table 4)
Table 3. Control Byte Format
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