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參數(shù)資料
| 型號： | MXA-256-1 |
| 英文描述： | Optoelectronic |
| 中文描述： | 光電 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 1530K |
| 代理商： | MXA-256-1 |
www.perkinelmer.com/opto
MXA-256-1, 2
Ev EOS/Odd EOS
The EvEOS and OdEOS are timing markers that indicate
the end of the even and odd readout cycle respectively.
These output pulses occur immediately after the end of
readout. The pulse is half the clock width and swings
from Vss to Vdd.
Ev Video1, 2 / Odd Video 1, 2
These are analog outputs of the multiplexer. These
outputs are low impedance op-amp outputs and
have a limited drive capability. They should be
buffered as close as possible to the package output . The
load on these outputs should not exceed 60 pF. Video 1
is the sample taken at the beginning of the integration and
Video 2 at the end of integration. The output voltage
swing is equal to Vref, which is from Vss+1. Please refer
to the timing diagrams for the timing of these video
signals.
Vref
This is the input voltage reference. The output voltage
swing is equal to Vref. The range of Vref voltage is 2.5V
to 3.5V, with current requirement of <5mA.
Power
Vss - Ground
Vdd - 5V, <50mA
Device Timing Parameters
Operating Conditions
Parameters
VDD
VSS
Vref
Clock
High
Low
Frequency
Duty Cycle
I
nt/Reset
High
Low
Cap Sel
Select
Deselect
Output
Impedance
Units
V
V
V
V
V
Hz
%
V
V
V
V
K
Minimum
4.90
2.5
10 x 10
3
45
Typical
5.00
0.00
3.00
VDD
VSS
50
VDD
VSS
VDD
VSS
2.00
Maximum
5.20
3.5
1 x 10
6
55
01-001:121201/10
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