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參數(shù)資料
| 型號： | MX805ALH |
| 英文描述： | RF/Baseband Circuit |
| 中文描述： | 射頻/基帶電路 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大?。?/td> | 532K |
| 代理商： | MX805ALH |
Sub-Audio Signaling Processor
5.2.6
Read NRZ RX Data Register – A/C 74
H
(7C
H
) followed by 1 byte Reply Data
Received NRZ data bits are organized into bytes and made available to the microcontroller via the Reply Data
line. As 8 bits are received into this register and interrupt is generated to indicate that a complete byte has
been received. This byte must be read before the arrival of the last (8
) bit of the next incoming byte. If this
in not done, an interrupt to indicate this condition will be generated and the previous RX data is discarded.
See Table 7.
Word synchronization is not provided. Byte synchronization and any codeword recognition will be performed
by the host microcontroller. The RX baud rate is set by writing to the CTCSS TX Frequency/NRZ Baud Rate
Register (73
H
/7B
H
). The first bit received is the first bit sent to the microcontroller.
This register is not affected by the General Reset Command (01H), and may adopt random configuration at
Power-Up.
5.2.7
Write to NRZ TX Data Register – A/C 75
H
(7D
H
) followed by 1 byte of Command Data.
A byte for transmission is loaded from the C-BUS Command Data line with the A/C. The first data bit
received via the C-BUS is transmitted first. The transmitter operation is non-inverting.
The first data byte loaded after the NRZ Encoder is enabled (Control Register) initiates the transmission
sequence and an interrupt will be generated when the NRZ TX Data Buffer is ready for the next data byte.
Subsequently, interrupts occur for every 8 bits transmitted.
Transmission is terminated, the TX Sub-Audio Output is placed at V
BIAS
, and a interrupt is generated if the
next byte is not loaded within 7 bit periods. See Table 7.
This register is not affected by the General Reset Command (01
H
), and may adopt any random configuration
at Power-Up.
5.2.8
Write to Gain Set Register – A/C 76
H
(7E
H
) followed by 1 byte of Command Data
5.2.8.1
Gain Set Register Settings:
The settings of this register control the CTCSS and NRZ signal level that is presented at the TX Sub-Audio
Output.
Bit 3, when enabled, is used to produce a pre-emphasis effect on the NRZ TX Data by increasing the gain of
the data bit before a level change (See Figure 8), by 1.72dB to make that data pulse level slightly more
positive (or negative). The signal level will be 1.72dB greater that that set by Bits 0 to 2. If the TX Sub-Audio
Output level is set to +2.58dB, the pre-emphasis level will be +4.3dB.
The pre-emphasis function will remain enabled until disabled by setting Bit 3 to a logic “0”. If this function
remains enabled when using the CTCSS Encoder, the output signal may be adversely affected. Therefore
this function should be enabled when in the NRZ Encode mode.
This register is not affected by the General Reset Command (01
H
), and may adopt any random configuration
at Power-Up.
Setting
7
6
5
4
Transmitted Bit 7 First
0
0
0
0
3
Pre-Emphasis Setting
1
0
1.72dB Gain Disabled
2
1
0
Tx Level Adjust Gain Setting
0
0
0
0
1
1
1
1
1
1
Table 10: Gain Set Register Settings
Page 17 of 24
MX805A
2001 MX-COM, Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
All trademarks and service marks are held by their respective companies.
Doc. # 20480116.005
Gain Setting
1.72dB Gain Enabled
0
0
1
1
0
0
1
0
1
0
1
0
1
0
-2.58dB
–1.72dB
–0.86dB
0dB
+0.86dB
+1.72dB
+2.58dB
Not Used
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相關(guān)代理商/技術(shù)參數(shù) |
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| MX805J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RF/Baseband Circuit |
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| MX806A | 制造商:CMLMICRO 制造商全稱:CML Microcircuits 功能描述:Audio Processor |
| MX806ADW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Audio Processor |
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