參數(shù)資料
型號: MX7847
英文描述: Complete.Dual.12-Bit Multiplying DAC with 8-Bit Bus Interface
中文描述: Complete.Dual.12位乘法DAC,具有8位總線接口
文件頁數(shù): 3/14頁
文件大?。?/td> 326K
代理商: MX7847
M
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +15V ±10%, V
SS
= -15V ±10%, V
CC
= +5V ±5%, V
GND
= V
DUTGND_ _
= 0, V
REF
_ _ _ _+ = +5V, V
REF
_ _ _ _- = -5V, R
L
= 5k
,
C
L
= 50pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
INTERFACE TIMING CHARACTERISTICS
(V
DD
= +15V ±10%, V
SS
= -15V ±10%, V
CC
= +5V ±5%, V
GND
= V
DUTGND_ _
= 0, V
REF
_ _ _ _+ = +5V, V
REF
_ _ _ _- = -5V, Figure 2a,
T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
CONDITIONS
k
μA
V
60
Input Impedance per DAC
Maximum Input Current per DAC
Input Range
DIGITAL INPUTS
±300
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Digital inputs = 0V or V
CC
μA
±1
±10
I
IN
-2
+2
Input Current
POWER SUPPLIES
V
4.75
5.25
10
V
CC
I
DD
V
CC
Digital Power Supply
Positive Supply Current
Negative Supply Current
Digital Supply Current
V
13.5
16.5
V
DD
V
DD
Analog Power-Supply
Range
V
-16.75
-13.5
V
SS
V
SS
Analog Power-Supply
Range
V
SS
= -15V ±5%
V
DD
= +15V ±5%
dB
90
R
L
=
(Note 2)
dB
R
L
=
90
PSRR,
V
OUT
/
V
DD
PSRR,
V
OUT
/
V
SS
mA
mA
8
10
0.5
I
SS
I
CC
mA
8
ns
0
t
4
t
5
t
6
ns
50
t
3
LDAC
Pulse Width Low
CS
Low to
WR
Low
CONDITIONS
ns
50
t
1
t
2
CS
Pulse Width Low
ns
50
WR
Pulse Width Low
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
ns
15
t
8
t
9
t
10
ns
0
t
7
Data Valid to
WR
Hold
Address Valid to
WR
Setup
ns
0
CS
High to
WR
High
ns
20
Data Valid to
WR
Setup
ns
0
Address Valid to
WR
Hold
(Note 1)
pF
10
C
IN
Input Capacitance
V
V
2.4
V
IH
V
IL
Input Voltage High
Input Voltage Low
0.8
DUTGND_ _ CHARACTERISTICS
(Figure 2b)
ns
300
CLR
Pulse-Activation Time
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