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參數(shù)資料
| 型號： | MX7847 |
| 英文描述： | Complete.Dual.12-Bit Multiplying DAC with 8-Bit Bus Interface |
| 中文描述： | Complete.Dual.12位乘法DAC，具有8位總線接口 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 326K |
| 代理商： | MX7847 |
M
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
10
______________________________________________________________________________________
This glitch/deglitch circuitry is enabled on the falling
edge of
LDAC
to remove the glitch from the R-2R DAC.
This enables the MX7841 to exhibit a fraction of the glitch
impulse energy of parts without the deglitching circuit.
Digital Inputs and Interface Logic
All digital inputs are compatible with both TTL and
CMOS logic. The MX7841 interfaces with microproces-
sors using a data bus at least 14 bits wide. The inter-
face is double buffered, allowing simultaneous
updating of all DACs. There are two latches for each
DAC (see the
Functional Diagram
): an input latch that
receives data from the data bus, and a DAC latch that
receives data from the input latch. Address lines A0,
A1, and A2 select which DAC’s input latch receives
data from the data bus as shown in Table 1. Both the
input latches and the DAC latches are transparent
when
CS
,
WR
, and
LDAC
are all low. Any change of
DB0–DB13 during this condition appears at the output
instantly. Transfer data from the input latches to the
DAC latches by asserting the asynchronous
LDAC
sig-
nal. Each DAC’s analog output reflects the data held in
its DAC latch. All control inputs are level triggered.
Table 2 is an interface truth table.
Input Write Cycle
Data can be latched or transferred directly to the DAC.
CS
and
WR
control the input latch, and
LDAC
transfers
information from the input latch to the DAC latch. The
input latch is transparent when
CS
and
WR
are low,
and the DAC latch is transparent when
LDAC
is low.
The address lines (A0, A1, A2) must be valid for the
duration that
CS
and
WR
are low (Figure 2a) to prevent
data from being inadvertently written to the wrong DAC.
Data is latched within the input latch when either
CS
or
WR
is high.
Loading the DACs
Taking
LDAC
high latches data into the DAC latches. If
LDAC
is brought low when
WR
and
CS
are low, the
DAC addressed by A0, A1, and A2 is directly con-
trolled by the data on DB0–DB13. This allows the maxi-
mum digital update rate; however, it is sensitive to any
glitches or skew in the input data stream.
Asynchronous Clear
The MX7841 has an asynchronous clear pin (
CLR
) that,
when asserted, sets all DAC outputs to the voltage pre-
sent on their respective DUTGND pins. Deassert
CLR
to
return the DAC output to its previous voltage. Note that
CLR
does not clear any of the internal digital registers.
See Figure 2b.
Applications Information
Multiplying Operation
The MX7841 can be used for multiplying applications.
Its reference accepts both DC and AC signals. Since
the reference inputs are unipolar, multiplying operation
is limited to two quadrants. See the graphs in the
Typical Operating Characteristics
for dynamic perfor-
mance of the DACs and output buffers.
Digital Code and
Analog Output Voltage
The MX7841 uses offset binary coding. A 14-bit two’s
complement code is converted to a 14-bit offset binary
code by adding 2
13
= 8192.
Output Voltage Range
For typical operation, connect DUTGND to signal ground,
V
REF
+ to +5V, and V
REF
- to -5V. Table 3 shows the rela-
tionship between digital code and output voltage.
A2
FUNCTION
DAC A input latch
0
DAC C input latch
0
DAC B input latch
0
DAC D input latch
0
DAC H input latch
1
DAC E input latch
1
DAC G input latch
1
DAC F input latch
1
A1
1
0
1
1
0
0
1
0
A0
1
0
0
1
1
0
0
1
CLR
DAC register transparent
FUNCTION
X
Input register transparent
X
Input register latched
X
Input register latched
X
DAC register latched
X
Outputs of DACs set to volt-
age defined by the DAC
register, the references,
and the corresponding
DUTGND_ _
1
Outputs of DACs at
DUTGND_ _
0
LD
0
X
X
X
1
1
X
WR
X
0
1
X
X
X
X
Table 1. MX7841 DAC Addressing
Table 2. Interface Truth Table
CS
X
0
X
1
X
X
X
X = Don’t care.
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