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參數(shù)資料
| 型號： | MX7841 |
| 英文描述： | Octal. 14-Bit Voltage-Output DAC with Parallel Interface |
| 中文描述： | 八進制。 14位電壓輸出DAC，具有并行接口 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 326K |
| 代理商： | MX7841 |
M
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
_______________________________________________________________________________________
9
_______________Detailed Description
Analog Section
The MX7841 contains eight 14-bit voltage-output DACs.
These DACs are inverted R-2R ladder networks that
convert 14-bit digital inputs into equivalent analog out-
put voltages, in proportion to the applied reference volt-
ages (Figure 1). The MX7841 has three positive
reference inputs (REF_ _ _ _+) and three negative refer-
ence inputs (REF_ _ _ _-). The difference from
REF_ _ _ _+ to REF_ _ _ _-, multiplied by two, sets the
DAC output span.
In addition to the differential reference inputs, the
MX7841 has four analog-ground input pins
(DUTGND_ _). When
CLR
is high (unasserted), the volt-
age on DUTGND_ _ offsets the DAC output voltage
range. If
CLR
is asserted, the output amplifier is forced
to the voltage present on DUTGND_ _.
Reference and DUTGND Inputs
All of the MX7841’s reference inputs are buffered with
precision amplifiers. This allows the flexibility of using
resistive dividers to set the reference voltages. Because
of the relatively high multiplying bandwidth of the refer-
ence input (188kHz), any signal present on the reference
pin within this bandwidth is replicated on the DAC output.
The DUTGND pins of the MX7841 are connected to the
negative source resistor (nominally 115k
) of the out-
put amplifier. The DUTGND pins are typically connect-
ed directly to analog ground. Each of these pins has an
input current that varies with the DAC digital code. If
the DUTGND pins are driven by external circuitry, bud-
get ±200μA per DAC for load current.
Output-Buffer Amplifiers
The MX7841’s voltage outputs are internally buffered by
precision gain-of-two amplifiers with a typical slew rate
of 1V/μs. With a full-scale transition at its output, the
typical settling time to ±1/2 LSB is 31μs. This settling
time does not significantly vary with capacitive loads
less than 10,000pF.
Output Deglitching Circuit
The MX7841’s internal connection from the DAC ladder
to the output amplifier contains special deglitch circuitry.
REF-
REF+
2R
2R
2R
2R
2R
OUT
DUTGND
2R
CLR
R
R
D0
D12
D13
Figure 1. DAC Simplified Circuit
V
OUT_
CLR
t
10
t
10
Figure 2b. Digital Timing Diagram
CS
WR
A0–A2
DB0–DB13
LDAC
NOTES:
1. ALL INPUT RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF
+5V. t
r
= t
f
= 5ns.
2.
MEASUREMENT REFERENCE LEVEL IS (V
INH
+ V
INL
) / 2.
IF LDAC IS ACTIVATED WHILE WR IS LOW, THEN LDAC MUST STAY LOW
FOR t
3
OR LONGER AFTER WR GOES HIGH.
(NOTE 3)
3.
t
1
t
2
t
8
t
9
t
6
t
7
t
4
t
5
t
3
t
3
Figure 2a. Digital Timing Diagram
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