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參數(shù)資料
| 型號(hào)： | MX7841 |
| 英文描述： | Octal. 14-Bit Voltage-Output DAC with Parallel Interface |
| 中文描述： | 八進(jìn)制。 14位電壓輸出DAC，具有并行接口 |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 326K |
| 代理商： | MX7841 |
The DAC digital code controls each leg of the 14-bit
R-2R ladder. A code of 0x0 connects all legs of the lad-
der to REF-, corresponding to a DAC output voltage
(V
DAC
) equal to REF-. A code of 0x3FFF connects all
legs of the ladder to REF+, corresponding to a V
DAC
approximately equal to REF+.
The output amplifier multiplies V
DAC
by 2, yielding an out-
put voltage range of 2
REF- to 2
REF+ (Figure 1).
Further manipulation of the output voltage span is accom-
plished by offsetting DUTGND. The output voltage of the
MX7841 is described by the following equation:
where DATA is the numeric value of the DAC’s binary
input code, and DATA ranges from 0 to 16,383
(2
14
- 1). The resolution of the MX7841, defined as
1 LSB, is described by the following equation:
(
Reference Selection
Because the MX7841 has precision buffers on its refer-
ence inputs, the requirements for interfacing to these
inputs are minimal. Select a low-drift, low-noise refer-
ence within the recommended REF+ and REF- voltage
ranges. The MX7841 does not require bypass capaci-
tors on its reference inputs. Add capacitors only if the
reference voltage source requires them to meet system
specifications.
Minimizing Output Glitch
The MX7841’s internal deglitch circuitry is enabled on
the falling edge of
LDAC
. Therefore, to achieve opti-
mum performance, drive
LDAC
low after the inputs are
either latched or steady state. This is best accom-
plished by having the falling edge of
LDAC
occur at
least 50ns after the rising edge of
CS
.
Power Supplies, Grounding,
and Bypassing
For optimum performance, use a multilayer PC board
with an unbroken analog ground. For normal operation,
connect the four DUTGND pins directly to the ground
plane. Avoid sharing the connections of these sensitive
pins with other ground traces.
As with any sensitive data-acquisition system, connect
the digital and analog ground planes together at a sin-
gle point, preferably directly underneath the MX7841.
Avoid routing digital signals underneath the MX7841 to
minimize their coupling into the IC.
For normal operation, bypass V
DD
and V
SS
with 0.1μF
ceramic chip capacitors to the analog ground plane. To
enhance transient response and capacitive drive capa-
bility, add 10μF tantalum capacitors in parallel with the
ceramic capacitors. Note, however, that the MX7841
does not require the additional capacitance for stability.
Bypass V
CC
with a 0.1μF ceramic chip capacitor to the
digital ground plane.
Power-Supply Sequencing
To guarantee proper operation of the MX7841, ensure
that power is applied to V
DD
before V
SS
and V
CC
. Also
ensure that V
SS
is never more than 300mV above
ground. To prevent this situation, connect a Schottky
diode between V
SS
and the analog ground plane, as
shown in Figure 3. Do not power up the logic input pins
LSB
REF
REF
2
14
=
+
)
2
V
2 V
V
DATA
2
V
V
OUT
REF
REF
14
REF
DUTGND
=
)
+
+
M
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
______________________________________________________________________________________
11
Note:
Output voltage is based on REF+ = +5V, REF- = -5V, and
DUTGND = 0.
GND
V
SS
SYSTEM GND
1N5817
MX7839
V
SS
V
SS
Figure 3. Schottky Diode Between V
SS
and GND
Table 3. Analog Voltage vs. Digital Code
INPUT CODE
OUTPUT
VOLTAGE (V)
11 1111 1111 1111
10 0000 0000 0000
01 0011 1011 0010
00 0000 0000 0001
00 0000 0000 0000
+9.998779
0
-3.845215
-9.998779
-10
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