參數(shù)資料
型號(hào)： MX29F1615
廠商： Macronix International Co., Ltd.
元件分類： DRAM
英文描述： The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述： 該CAT24FC02是一個(gè)2 KB的EEPROM的國(guó)內(nèi)256個(gè)8位每字舉辦的串行CMOS
文件頁(yè)數(shù)： 6/26頁(yè)
文件大?。?/td> 337K
代理商： MX29F1615
6
P/N: PM0615
REV. 1.1, JUN. 15, 2001
MX29F1615
WRITE OPERATIONS
Commands are written to the COMMAND INTERFACE
REGISTER (CIR) using standard microprocessor write
timings. The CIR serves as the interface between the
microprocessor and the internal chip operation. The CIR
can decipher Read Array, Read Silicon ID, Erase and
Program command. In the event of a read command, the
CIR simply points the read path at either the array or the
silicon ID, depending on the specific read command
given. For a program or erase cycle, the CIR informs the
write state machine that a program or erase has been
requested. During a program cycle, the write state
machine will control the program sequences and the CIR
will only respond to status reads. During a sector/chip
erase cycle, the CIR will respond to status reads and
erase suspend. After the write state machine has
completed its task, it will allow the CIR to respond to its full
command set. The CIR stays at read status register
mode until the microprocessor issues another valid
command sequence.
Device operations are selected by writing commands into
the CIR. Table 3 below defines 16 Mbit flash command.
TABLE 3. COMMAND DEFINITIONS(Word-Wide Mode, BYTE/VPP=VHH)
Command
Sequence
Bus Write
Cycles Req'd
First Bus
Write Cycle
Second Bus
Write Cycle
Third Bus
Write Cycle
Fourth Bus
Read/Write Cycle
Fifth Bus
Write Cycle
Sixth Bus
Write Cycle
Read/
Reset
4
Silicon
ID Read
4
Page
Program
4
Chip
Erase
6
Read
Clear
Status Reg. Status Reg.
4
3
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
5555H
AAH
2AAAH
55H
5555H
F0H
RA
RD
5555H
AAH
2AAAH
55H
5555H
90H
00H/01H
C2H/6BH
5555H
AAH
2AAAH
55H
5555H
A0H
PA
PD
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
5555H
10H
5555H
AAH
2AAAH
55H
5555H
70H
X
SRD
5555H
AAH
2AAAH
55H
5555H
50H
Notes:
1. Address bit A15 -- A19 = X = Don't care for all address commands except for Program Address(PA).
5555H and 2AAAH address command codes stand for Hex number starting from A0 to A14.
2. Bus operations are defined in Table 2.
3. RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the CE pulse.
4. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of CE.
SRD = Data read from status register.
5. Only Q0-Q7 command data is taken, Q8-Q15 = Don't care.
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MX29F200BMC-12 制造商:MCNIX 制造商全稱:Macronix International 功能描述:2M-BIT [256Kx8/128Kx16] CMOS FLASH MEMORY
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MX29F200BMI-12 制造商:MCNIX 制造商全稱:Macronix International 功能描述:2M-BIT [256Kx8/128Kx16] CMOS FLASH MEMORY
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