參數(shù)資料
型號： MX26L6420XAI-12
廠商： Macronix International Co., Ltd.
英文描述： 64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM
中文描述： 6400位[4米× 16]的CMOS多重一次性可編程存儲器
文件頁數(shù)： 12/39頁
文件大?。?/td> 1253K
代理商： MX26L6420XAI-12
12
P/N:PM0823
REV. 0.5, JAN. 29, 2002
MX26L6420
ACCELERATED PROGRAM OPERATIONS
The device offers accelerated program operations through
the ACC pin. When the system asserts V
HH
on the ACC
pin, the device automatically bypass the two "Unlock"
write cycle. The device uses the higher voltage on the
ACC pin to accelerate the operation. Note that the ACC
pin must not be at V
HH
any operation other than accelerated
programming, or device damage may result.
SETUP AUTOMATIC CHIP ERASE
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cycles
are then followed by the chip erase command 10H.
The MX26L6420 contains a Silicon-ID-Read operation to
supplement traditional PROM programming methodology.
The operation is initiated by writing the read silicon ID
command sequence into the command register. Follow-
ing the command write, a read cycle with A6=VIL,
A1=VIL, A0=VIL retrieves the manufacturer code of C2H.
A read cycle with A6=VIL, A1=VIL, A0=VIH returns the
device code of 22FCH for MX26L6420.
AUTOMATIC CHIP ERASE COMMAND
The device does not require the system to preprogram
prior to erase. The Automatic Erase algorithm automati-
cally preprograms and verifies the entire memory for an
all zero data pattern prior to electrical erase. The system
is not required to provide any controls or timings during
these operations. Table 4 shows the address and data
requirements for the chip erase command sequence.
Any commands written to the chip during the Automatic
Erase algorithm are ignored. Note that a hardware reset
during the chip erase operation immediately terminates
the operation. The Chip Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
The system can determine the status of the erase op-
eration by using Q7, Q6. See "Write Operation Status"
for information on these status bits. When the Automatic
Erase algorithm is complete, the device returns to read-
ing array data and addresses are no longer latched.
Figure 5 illustrates the algorithm for the erase opera-
tion.See the Erase/Program Operations tables in "AC
Characteristics" for parameters, and to Figure 4 for tim-
ing diagrams.
TABLE 5. SILICON ID CODE
Pins
A0
A1
A6
Q15
|
Q8
00H
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Code(Hex)
Manufacture code
VIL
VIL
VIL
1
1
0
0
0
0
1
0
00C2H
Device code for MX26L6420 VIH
VIL
VIL
22H
1
1
1
1
1
1
1
0
22FCH
相關(guān)PDF資料
PDF描述
MX26L6420MI-12 64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM
MX26L6420XAC-12 64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM
MX26L6420XAC-90 64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM
MX26L6420XAI-90 64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM
MX26L6420XBI-12 64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MX26L6420XAI-90 制造商:MCNIX 制造商全稱:Macronix International 功能描述:64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM
MX26L6420XBC-12 制造商:MCNIX 制造商全稱:Macronix International 功能描述:64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM
MX26L6420XBC-90 制造商:MCNIX 制造商全稱:Macronix International 功能描述:64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM
MX26L6420XBI-12 制造商:MCNIX 制造商全稱:Macronix International 功能描述:64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM
MX26L6420XBI-90 制造商:MCNIX 制造商全稱:Macronix International 功能描述:64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*