- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380535 > MX26L6420XAI-12 (Macronix International Co., Ltd.) 64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM PDF資料下載
參數(shù)資料
| 型號： | MX26L6420XAI-12 |
| 廠商： | Macronix International Co., Ltd. |
| 英文描述： | 64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM |
| 中文描述： | 6400位[4米× 16]的CMOS多重一次性可編程存儲器 |
| 文件頁數(shù)： | 10/39頁 |
| 文件大小： | 1253K |
| 代理商： | MX26L6420XAI-12 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁
10
P/N:PM0823
REV. 0.5, JAN. 29, 2002
MX26L6420
SOFTWARE COMMAND DEFINTIONS
Device operations are selected by writing specific ad-
dress and data sequences into the command register.
Writing incorrect address and data values or writing them
in the improper sequence will reset the device to the
read mode. Table 4 defines the valid register command
sequences. Either of the two reset command sequences
Legend:
X=Don't care
RA=Address of the memory location to be read.
RD=Data read from location RA during read operation.
PA=Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE or
CE pulse.
PD=Data to be programmed at location PA. Data is
latched on the rising edge of WE or CE pulse.
will reset the device(when applicable).
All addresses are latched on the falling edge of WE or
CE, whichever happens later. All data are latched on ris-
ing edge of WE or CE, whichever happens first.
First Bus
Second Bus Third Bus
Fourth Bus
Fifth Bus
Sixth Bus
Command
Bus
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Addr
Data
Addr
Data Addr
Data Addr
Data
Addr
Data Addr Data
Read(Note 5)
1
RA
RD
Reset(Note 6)
1
XXX
F0
Autoselect(Note 7)
Manufacturer ID
4
555
AA
2AA
55
555
90
X00
C2
Device ID
4
555
AA
2AA
55
555
90
X01
22FC
Secured Sector
4
555
AA
2AA
55
555
90
x03
see
Factory Protect
Note9
Enter Secured Silicon
3
555
AA
2AA
55
555
88
Sector
Exit Secured Silicon
4
555
AA
2AA
55
555
90
xxx
00
Sector
Porgram
4
555
AA
2AA
55
555
A0
PA
PD
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
TABLE4. MX26L6420
COMMAND DEFINITIONS
Notes:
1.See Table 1 for descriptions of bus operations.
2.All values are in hexadecimal.
3.Except when reading array or autoselect data, all bus cycles are write operation.
4.Address bits are don't care for unlock and command cycles, except when PA is required.
5.No unlock or command cycles required when device is in read mode.
6.The Reset command is required to return to the read mode when the device is in the autoselect mode or if Q5 goes
high.
7.The fourth cycle of the autoselect command sequence is a read cycle.
8.In the third and fourth cycles of the command sequence, set A21=0.
8.Command is valid when device is ready to read array data or when device is in autoselect mode.
9.The data is 88h for factory locked and 08h for non-factory locked.
相關PDF資料 |
PDF描述 |
|---|---|
| MX26L6420MI-12 | 64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM |
| MX26L6420XAC-12 | 64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM |
| MX26L6420XAC-90 | 64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM |
| MX26L6420XAI-90 | 64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM |
| MX26L6420XBI-12 | 64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MX26L6420XAI-90 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM |
| MX26L6420XBC-12 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM |
| MX26L6420XBC-90 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM |
| MX26L6420XBI-12 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM |
| MX26L6420XBI-90 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM |
發(fā)布緊急采購，3分鐘左右您將得到回復。