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參數(shù)資料
| 型號： | MX10EXAQCG |
| 廠商： | MACRONIX INTERNATIONAL CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | XA 16-bit Microcontroller Family 64K Flash/2K RAM, Watchdog, 2UARTs |
| 中文描述： | 16-BIT, FLASH, 30 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 44/55頁 |
| 文件大?。?/td> | 488K |
| 代理商： | MX10EXAQCG |
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44
P/N:PM0625
Specifications subject to change without notice, contact your sales representatives for the most update information.
REV. 1.0, JUL. 01, 2005
MX10EXA
AC ELECTRICAL CHARACERISTICS (5V)
VDD = 4.5V to 5.5V; Tamb = 0 to +70
°
C for commercial - 40
O
C to +85
O
C for Industrial
SYMBOL FIGURE
PARAMETER
VARIABLE CLOCK
MIN
UNIT
MAX
External Clock
f
C
t
C
t
CHCX
t
CLCX
t
CLCH
t
CHCL
Address Cycle
t
CRAR
t
LHLL
t
AVLL
t
LLAX
Code Read Cycle
t
PLPH
t
LLPL
t
AVIVA
26
26
26
26
26
26
Oscillator frequency
Clock period and CPU timing cycle
Clock high time
Clock low time
Clock rise time
Clock fall time
0
1/ f
C
t
C
* 0.5
7
t
C
* 0.4
7
30
MHz
ns
ns
ns
ns
ns
5
5
25
20
20
20
Delay from clock rising edge to ALE rising edge
ALE pulse width (programmable)
Address valid to ALE de-asserted (set-up)
Address hold after ALE de-asserted
5
(V1 * t
C
)-6
(V1 * t
C
)-12
(t
C
/2)-10
46
ns
ns
ns
ns
20
20
20
PSEN pulse width
ALE de-asserted to PSEN asserted
Address valid to instruction valid, ALE cycle
(access time)
Address valid to instruction valid, non-ALE cycle
(access time)
PSEN asserted to instruction valid
(enable time)
Instruction hold after PSEN de-asserted
(V2 * t
C
)-10
(t
C
/2)-7
ns
ns
ns
(V3 * t
C
)-36
t
AVIVB
21
(V4 * t
C
)-29
ns
t
CPLIV
20
(V2 * t
C
)-29
ns
t
PXIX
20
0
ns
t
PXIZ
20
Bus 3-State after PSEN de-asserted
(disable time)
Hold time of unlatched part of address after
instruction latched
t
C
- 8
ns
t
IXUA
20
0
ns
Data Read Cycle
t
RLRH
t
LLRL
t
AVDVA
22
22
22
RD pulse width
ALE de-asserted to RD asserted
Address valid to data input valid, ALE cycle
(access time)
Address valid to data input valid, non-ALE cycle
(access time)
RD low to valid data in, enable time
Data hold time after RD de-asserted
Bus 3-State after RD de-asserted (disable time)
Hold time of unlatched part of address after
data latched
(V7 * t
C
)-10
(t
C
/2)-7
ns
ns
ns
(V6 * t
C
)-36
t
AVDVB
23
(V5 * t
C
)-29
ns
t
RLDV
t
RHDX
t
RHDZ
t
DXUA
22
22
22
22
(V7 * t
C
)-29
ns
ns
ns
ns
0
t
C
-8
0
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| MX10EXAUC | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:XA 16-bit Microcontroller Family 64K Flash/2K RAM, Watchdog, 2UARTs |
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| MX10F201FC | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:High-Performance and Low Power Microcontroller designed for Use Many Applications |
| MX10FMAXDPC | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:SINGLE-CHIP 8-BIT MICROCONTROLLER |
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