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參數(shù)資料
| 型號： | MWS5101ADL3 |
| 廠商： | INTERSIL CORP |
| 元件分類： | DRAM |
| 英文描述： | 256-Word x 4-Bit LSI Static RAM |
| 中文描述： | 256 X 4 STANDARD SRAM, 350 ns, CDIP22 |
| 封裝： | SIDE BRAZED, CERAMIC, DIP-22 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 41K |
| 代理商： | MWS5101ADL3 |
6-59
Dynamic Electrical Specifications
at T
A
= 0
o
C to +70
o
C, V
DD
= 5V
±
5%
PARAMETER
SYMBOL
LIMITS
(NOTE 1)
UNITS
L2 TYPES
L3 TYPES
(NOTE 2)
MIN
(NOTE 3)
TYP
MAX
(NOTE 2)
MIN
(NOTE 3)
TYP
MAX
READ CYCLE TIMES (FIGURE 1)
Read Cycle
t
RC
250
-
-
350
-
-
ns
Access from Address
t
AA
-
150
250
-
200
350
ns
Output Valid from Chip Select 1
t
DOA1
-
150
250
-
200
350
ns
Output Valid from Chip Select 2
t
DOA2
-
150
250
-
200
350
ns
Output Valid from Output Disable
t
DOA3
-
-
110
-
-
150
ns
Output Hold from Chip Select 1
t
DOH1
20
-
-
20
-
-
ns
Output Hold from Chip Select 2
t
DOH2
20
-
-
20
-
-
ns
Output Hold from Output Disable
t
DOH3
20
-
-
20
-
-
ns
WRITE CYCLE TIMES (FIGURE 2)
Write Cycle
t
WC
300
-
-
400
-
-
ns
Address Setup
t
AS
110
-
-
150
-
-
ns
Write Recovery
t
WR
40
-
-
50
-
-
ns
Write Width
t
WRW
150
-
-
200
-
-
ns
Input Data Setup Time
t
DS
150
-
-
200
-
-
ns
Data in Hold
t
DH
40
-
-
50
-
-
ns
Chip Select 1 Setup
t
CS1S
110
-
-
150
-
-
ns
Chip Select 2 Setup
t
CS2S
110
-
-
150
-
-
ns
Chip Select 1 Hold
t
CS1H
0
-
-
0
-
-
ns
Chip Select 2 Hold
t
CS2H
0
-
-
0
-
-
ns
Output Disable Setup
t
ODS
110
-
-
150
-
-
ns
NOTES:
1. MWS5101: t
R
, t
F
= 20ns, V
IH
= 0.7V
DD
, V
IL
= 0.3V
DD
; C
L
= 100pF and MWS5101A: t
R
, t
F
= 20ns, V
IH
= 2.2V, V
IL
= 0.65V; C
L
= 50pF
and 1 TTL Load.
2. Time required by a limit device to allow for the indicated function.
3. Typical values are for T
A
= 25
o
C and nominal V
DD.
MWS5101, MWS5101A
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