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參數(shù)資料
| 型號(hào)： | MWS5101EL2 |
| 廠商： | INTERSIL CORP |
| 元件分類： | DRAM |
| 英文描述： | POT 20K OHM 3/8 SQ CERM SL MT |
| 中文描述： | 256 X 4 STANDARD SRAM, 250 ns, PDIP22 |
| 封裝： | PLASTIC, DIP-22 |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大?。?/td> | 41K |
| 代理商： | MWS5101EL2 |
6-56
Features
Industry Standard Pinout
Very Low Operating Current. . . . . . . . . . . . . . . . . . 8mA
at V
DD
= 5V and Cycle Time = 1
μ
s
Two Chip Select Inputs Simple Memory Expansion
Memory Retention for Standby. . . . . . . . . . . . . 2V (Min)
Battery Voltage
Output Disable for Common I/O Systems
Three-State Data Output for Bus Oriented Systems
Separate Data Inputs and Outputs
TTL Compatible (MWS5101A)
Pinout
MWS5101, MWS5101A
(PDIP, SBDIP)
TOP VIEW
Description
The MWS5101 and MWS5101A are 256 word by 4-bit static
random access memories designed for use in memory
systems where high speed, very low operating current, and
simplicity in use are desirable. They have separate data
inputs and outputs and utilize a single power supply of 4V to
6.5V. The MWS5101 and MWS5101A differ in input voltage
characteristics (MWS5101A is TTL compatible).
Two Chip Select inputs are provided to simplify system
expansion. An Output Disable control provides Wire-OR
capability and is also useful in common Input/Output
systems by forcing the output into a high impedance state
during a write operation independent of the Chip Select input
condition. The output assumes a high impedance state
when the Output Disable is at high level or when the chip is
deselected by CS1 and/or CS2.
The high noise immunity of the CMOS technology is
preserved in this design. For TTL interfacing at 5V operation,
excellent system noise margin is preserved by using an
external pull-up resistor at each input.
For applications requiring wider temperature and operating
voltage ranges, the mechanically and functionally equivalent
static RAM, CDP1822 may be used.
The MWS5101 and MWS5101A types are supplied in 22
lead hermetic dual-in-line, sidebrazed ceramic packages (D
suffix), in 22 lead dual-in-line plastic packages (E suffix), and
in chip form (H suffix).
Ordering Information
1
11
10
9
8
7
6
5
3
2
4
22
12
13
14
15
16
17
18
19
21
20
A2
A1
A0
A5
A6
A7
DI1
V
SS
DO1
DI2
A4
CSI
O.D.
CS2
R/W
DO4
DI4
DO3
DI3
DO2
A3
V
DD
PACKAGE
TEMP. RANGE
0
o
C to +70
o
C
MWS5101
350ns
MWS5101A
350ns
PKG. NO.
250ns
250ns
PDIP
Burn-In
MWS5101EL2
MWS5101ELS
MWS5101AEL2
MWS5101AEL3
E22.4
MWS5101AEL3X E22.4
SBDIP
Burn-In
0
o
C to +70
o
C
-
MWS5101DL3X
-
MWS5101ADL3
D22.4A
D22.4A
March 1997
MWS5101,
MWS5101A
256-Word x 4-Bit
LSI Static RAM
File Number
1106.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MWS5101ELS | 256-Word x 4-Bit LSI Static RAM |
| MWS5114 | 1024-Word x 4-Bit LSI Static RAM |
| MWS5114D2 | 1024-Word x 4-Bit LSI Static RAM |
| MWS5114D3 | 1024-Word x 4-Bit LSI Static RAM |
| MWS5114D3X | 1024-Word x 4-Bit LSI Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MWS5101EL2X | 制造商:Harris Corporation 功能描述: |
| MWS5101ELS | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:256-Word x 4-Bit LSI Static RAM |
| MWS5114 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:1024-Word x 4-Bit LSI Static RAM |
| MWS5114 DIE | 制造商:Harris Corporation 功能描述: |
| MWS5114_1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:1024-Word x 4-Bit LSI Static RAM |
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