
MVTX2601
Data Sheet
17
Zarlink Semiconductor Inc.
5.6 Port Based VLAN
An administrator can use the PVMAP Registers to configure the MVTX2601 for port-based VLAN. For example,
ports 1-3 might be assigned to the Marketing VLAN, ports 4-6 to the Engineering VLAN, and ports 7-9 to the
Administrative VLAN. The MVTX2601 determines the VLAN membership of each packet by noting the port on
which it arrives. From there, the MVTX2601 determines which outgoing port(s) is/are eligible to transmit each
packet, or whether the packet should be discarded.
Table 2 - PVMAP Register
For example, in the above table, a "
1"
denotes that an outgoing port is eligible to receive a packet from an incoming
port. A
0
(zero) denotes that an outgoing port is not eligible to receive a packet from an incoming port.
In this example:
Data packets received at port #0 are eligible to be sent to outgoing ports 1 and 2
Data packets received at port #1 are eligible to be sent to outgoing ports 0, and 2
Data packets received at port #2 are not eligible to be sent to ports 0 and 1
5.7 Memory Configurations
The MVTX2601 supports the following memory configurations. It supports 1 M and 2 M configurations.
Destination Port Numbers Bit Map
Port Registers
23
…
2
1
0
Register for Port #0
PVMAP00_0[7:0] to PVMAP00_2[7:0]
0
1
1
0
Register for Port #1
PVMAP01_0[7:0] to PVMAP01_2[7:0]
0
1
0
1
Register for Port #2
PVMAP02_0[7:0] to PVMAP02_2[7:0]
0
0
0
0
…
Register for Port #23
PVMAP23_0[7:0] to PVMAP23_2[7:0]
0
0
0
0
Configuration
1 M
(Bootstrap pin
TSTOUT7 = open)
2 M
(Bootstrap pin
TSTOUT7 = pull down)
Connections
Single Layer
(Bootstrap pin
TSTOUT13 = open)
Two 128 K x 32
SRAM/bank
or
One 128 K x 64 SRAM/bank
Two 256 K x 32
SRAM/bank
Connect 0E# and WE#
Double Layer
(Bootstrap pin
TSTOUT13 = pull down)
NA
Four 128 K x 32
SRAM/bank
or
Two 128 K x 64 SRAM/bank
Connect 0E0# and WE0#
Connect 0E1# and WE1#
Table 3 - Supported Memory Configurations (SBRAM Mode)