參數(shù)資料
型號： MVTX2601
廠商： Zarlink Semiconductor Inc.
英文描述： Unmanaged 24-Port 10/100 Mbps Ethernet Switch
中文描述： 非托管的24端口10/100 Mbps以太網(wǎng)交換機(jī)
文件頁數(shù)： 10/91頁
文件大?。?/td> 686K
代理商： MVTX2601
MVTX2601
Data Sheet
10
Zarlink Semiconductor Inc.
2.0 System Configuration
2.1 Configuration Mode
The MVTX2601 can be configured by EEPROM (24C02 or compatible) via an I
2
C interface at boot time or via a
synchronous serial interface during operation.
2.2 I
2
C Interface
The I
2
C interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL line carries the
control signals that facilitate the transfer of information from EEPROM to the switch. Data transfer is 8-bit serial and
bidirectional, at 50 Kbps. Data transfer is performed between master and slave IC using a request /
acknowledgment style of protocol. The master IC generates the timing signals and terminates data transfer.
Figure 2 depicts the data transfer format.
Figure 2 - Data Transfer Format for I
2
C Interface
2.2.1 Start Condition
Generated by the master (in our case, the MVTX2601). The bus is considered to be busy after the Start condition is
generated. The Start condition occurs if while the SCL line is High, there is a High-to-Low transition of the SDA line.
Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High
period of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the I
2
C bus is
free, both lines are High.
2.2.2 Address
The first byte after the Start condition determines which slave the master will select. The slave in our case is the
EEPROM. The first seven bits of the first data byte make up the slave address.
2.2.3 Data Direction
The eighth bit in the first byte after the Start condition determines the direction (R/W) of the message. A master
transmitter sets this bit to W; a master receiver sets this bit to R.
2.2.4 Acknowledgment
Like all clock pulses, the acknowledgment-related clock pulse is generated by the master. However, the transmitter
releases the SDA line (High) during the acknowledgment clock pulse. Furthermore, the receiver must pull down the
SDA line during the acknowledge pulse so that it remains stable Low during the High period of this clock pulse. An
acknowledgment pulse follows every byte transfer.
If a slave receiver does not acknowledge after any byte, then the master generates a Stop condition and aborts the
transfer.
If a master receiver does not acknowledge after any byte, then the slave transmitter must release the SDA line to let
the master generate the Stop condition.
2.2.5 Data
After the first byte containing the address, all bytes that follow are data bytes. Each byte must be followed by an
acknowledge bit. Data is transferred MSB first.
START
SLAVE ADDRESS
R/W
ACK
DATA 1 (8 bits)
ACK
DATA 2
ACK
DATA M
ACK
STOP
相關(guān)PDF資料
PDF描述
MVTX2601AG Unmanaged 24-Port 10/100 Mbps Ethernet Switch
MVTX2602 Managed 24 Port 10/100 Mbps Ethernet Switch
MVTX2602AG Managed 24 Port 10/100 Mbps Ethernet Switch
MVTX2603 Unmanaged 24-Port 10/100 Mb + 2-Port 1 Gb Ethernet Switch
MVTX2603AG Unmanaged 24-Port 10/100 Mb + 2-Port 1 Gb Ethernet Switch
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MVTX2601A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Unmanaged 24 port 10/100Mb Ethernet switch
MVTX2601AG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Unmanaged 24-Port 10/100 Mbps Ethernet Switch
MVTX2601AG2 制造商:Microsemi Corporation 功能描述:
MVTX2602 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Managed 24 Port 10/100 Mbps Ethernet Switch
MVTX2602A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MVTX260x Port Mirroring
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