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參數(shù)資料
| 型號： | MUPA64K16-15TJI |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP128 |
| 封裝： | LQFP-128 |
| 文件頁數(shù)： | 9/19頁 |
| 文件大?。?/td> | 380K |
| 代理商： | MUPA64K16-15TJI |
MUPA64K16 Alto Priority Queue Scheduler
MUSIC Semiconductors Confidential
17
Rev 0.3 Draft
Electrical Characteristics
Absolute Maximum Ratings
Supply Voltage: VDD = 1.98Volts
Supply Voltage: VDDQ = 3.6Volts
Voltage on all other pins: 5.5Volts
Storage Temperature:
NOTE: Stresses exceeding those listed under Absolute Maximum Ratings may induce failure.
Exposure to absolute maximum ratings for extended periods may reduce reliability.
Functionality at or above these conditions is not implied. All voltages referenced to GND (Vcc).
Table 14: DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
VDD
Operating Supply Voltage
1.62
1.8
1.98
Volts
VDDQ
Operating Supply Voltage
3.0
3.3
3.6
Volts
VIH
Input High Voltage
2.0
5.5
Volts
VIL
Input Low Voltage
-0.3
0.8
Volts
VOH
Output High Voltage
2.4
Volts
VOL
Output High Voltage
0.4
Volts
IOH
Output High Current
TBD
IOL
Output Low Current
TBD
IIZ
Input Leakage Current
+/- 10
+/- 1000
nA
IOZ
Output Leakage Current
+/- 10
+/- 1000
nA
Table 15: AC Characteristics
Symbol
Description
Min
Typ
Max
Unit
tCLK
Maximum clock frequency
66
MHz
tCKHI
CLK high pulse: worst-case 40%/60% duty cycle
6.0
9.0
ns
tCKLO
CLK low pulse: worst-case 40%/60% duty cycle
6.0
9.0
ns
tSUCS
Setup time for Chip Select input (/CS)
3.0
ns
tHDCS
Hold time for Chip Select input (/CS)
0.5
ns
tSUWR
Setup time for Write input (/WR)
3.4
ns
tHDWR
Hold time for Write input (/WR)
0.5
ns
tSUREG
Setup time for REG[2:0] inputs
3.7
ns
tHDREG
Hold time for REG[2:0] inputs
0.5
ns
tSUPQ
Setup time for PQ[3:0] inputs
4.5
ns
tHDPQ
Hold time for PQ[3:0] inputs
0.5
ns
tSUDQ
Setup time for DQ[31:0] bus
4.0
ns
tHDDQ
Hold time for DQ[31:0] bus
0.5
ns
tDOUT
Clock to valid Data Out
9.6
ns
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