參數(shù)資料
型號： MULTISYNCFE750
英文描述： Monitor_ICs:HD6433577 LA7841 BA9761F MQ571 XC13289LSP LSC3820P2 uPD61882A
中文描述： Monitor_ICs：HD6433577 LA7841 BA9761F MQ571 XC13289LSP LSC3820P2 uPD61882A
文件頁數(shù)： 27/52頁
文件大?。?/td> 517K
代理商： MULTISYNCFE750
MON08 Multilink User Manual
27
P&E
Microcomputer
Systems, Inc.
MON08 MULTILINK
The user must pull up the RESET line to target VDD with an external resistor.
The target IRQ line is directly connected to the Pin 6 of the target MON08
Header.
PORTA0 from the target processor is connected to the target MON08 Header
Pin 8, acting as the communications line. The MON08 MULTILINK pulls up
this signal with a 10K Ohm resistor to the target VDD.
PORTA1 and PORTA4 are used for entering monitor mode. By default the user
may directly bring these signals out to the target MON08 Header.
Alternatively, the user may pull up PORTA1 and pull down PORTA4. In which
case the user does not need to connect these signals to the target MON08
Header. The clock division is fixed Div 4.
Please note that in Stand-Alone programming mode the MON08 MULTILINK
will calculate the proper trim value for the device being programmed and
program this trim value to $FFC0.
3.25
68HC908RF
Figure 3-25: 68HC908RF Family MON08 Pinout
The target GND is connected to the Pin 2 of the target MON08 Header.
The target RESET line is directly connected to the Pin 4 of the target MON08
Header.
Alternatively, the user may pull up the RESET line to target VDD. In which
case the user does not need to connect this signal to the target MON08 Header.
The target IRQ line is directly connected to the Pin 6 of the target MON08
Header.
PORTA0 from the target processor is connected to the target MON08 Header
Pin 10, acting as the communications line. The MON08 MULTILINK pulls up
this signal with a 10K Ohm resistor to the target VDD.
PORTB0 and PORTB2 are used for entering monitor mode. By default the user
may directly bring these signals out to the target MON08 Header.
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