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參數(shù)資料
| 型號： | MUAC4K64-90TDC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 27/32頁 |
| 文件大?。?/td> | 504K |
| 代理商： | MUAC4K64-90TDC |
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MUAC Routing CoProcessor (RCP) Family
Pin Descriptions
4
Rev. 4
PIN DESCRIPTIONS
Note: Signal names that start with a slash (“/”) are active LOW. All signals are 3.3V CMOS level. Never leave inputs floating. The
CAM architecture draws large currents during compare operations, mandating the use of good layout and bypassing techniques. Refer
to the Electrical Characteristics section for more information.
DQ31–0 (Data Bus, Three-state, Common
Input/ Output)
The DQ31–0 lines convey data to and from the MUAC
RCP. When the /E input is HIGH the DQ31–0 lines are
held in their high-impedance state. The /W input
determines whether data flows to or from the device on the
DQ31–0 lines. The source or destination of the data is
determined by the AC bus, DSC, and the /AV line. During
a Write cycle, data on the DQ31–0 lines is registered by
the falling edge of /E.
AC12–0/AC11–0 (Address/Control Bus,
Input)
When Hardware control is selected, the AC bus conveys
address or control information to the MUAC RCP,
depending on the state of the /AV input. When /AV is
LOW then the AC bus carries an address; when /AV is
HIGH the AC bus carries control information. Data on the
AC bus is registered by the falling edge of /E. When
software control is selected, the state of the AC bus does
not affect the operation of the device.
DSC (Data Segment Control, Input)
When DQ bus access to a 64 bit register or memory word
is performed, the DSC input determines whether bits 31–0
(DSC LOW) or bits 63–32 (DSC HIGH) are accessed.
Access to 32 bit registers require that DSC be held LOW.
AA12–0/AA11–0 (Active Address, Output)
The AA bus conveys the Match address, the Next Free
address, or Random Access address, depending on the
most recent memory cycle. The /OE input enables the AA
bus; when the /OE input is HIGH, the AA bus is in its
high-impedance state; when /OE is LOW the AA bus is
active. In a vertically cascaded system after a Comparison
cycle, Write at Next Free Address cycle or Read/Write at
Highest-Priority match, only the highest-priority device
will enable its AA bus, regardless of the state of the /OE
input. In the event of a mismatch in the Address Database
after a Compare cycle, or after a Write at Next Free
Address
cycle
into
an
already
full
system,
the
lowest-priority device will drive the AA bus with all 1s.
The AA bus is latched when /E is LOW, and are free to
change only when /E is HIGH.
Figure 3: MUAC RCP Pinout
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
81
31
10 0
99
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
32
TCLK
TMS
TDI
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
VSS
DQ8
DQ9
DQ10
DQ11
VDD
DQ12
DQ13
DQ14
DQ15
VSS
AC11
AC10
AC9
AC8
AC7
AC6
VDD
AC5
AC4
AC3
AC2
AC1
AC0
TDO
AA12/NC*
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
/E
/W
/CS1
/CS2
/OE
VSS
/AV
/VB
/RESET
/TRST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
AA12/NC*
AA8
VSS
AA7
AA6
AA5
AA4
VDD
AA3
AA2
AA1
AA0
VSS
/MF
/FF
VDD
/M
I
/FI
VSS
/MM
DSC
PA3
PA2
PA1
PA0
AA10
AA9
AA11
MUAC RCP
100-Pin TQFP
(Top View)
* NC on MUAC4K64
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