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參數(shù)資料
| 型號： | MUAA8K80-20QGC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 13/18頁 |
| 文件大?。?/td> | 332K |
| 代理商： | MUAA8K80-20QGC |
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When DINREADY is HIGH, the synchronous port
accepted the current operation. This is affected by the
priority set for the DIN port and the processor port. Note,
DINREADY may be LOW for up to 800 CLK periods
after /RESET is taken HIGH. The JTAG interface is able
to set DINREADY to HIGH-Z. Active HIGH.
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DOUT[31:0] is the synchronous port data output. Data is
read out right aligned, least significant word first. The
address index (bits 25–0), SWEX flag (bit 26), PWEX flag
(bit 27), LQUEUE flag (bit 28), AQUEUE flag (bit 29),
Sync Port Match flag (bit 30), and Full flag (bit 31) may
also be read from this port before or after operation data
depending on configuration.
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/DOUTVALID indicates when new data is available at the
synchronous output port. /DOUTVALID is active LOW
for one CLK cycle. /DOUTVALID may be configured to
become active on the same clock as new DOUT becomes
valid or the CLK before. The JTAG interface is able to set
/DOUTVALID to HIGH-Z.
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/OE is the DOUT High Impedance control.
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/DOUTE is the DOUT enable control. When the DOUT
data word is configured to be wider than the output port
then this strobe enables the next word(s) of the DOUT data
onto the DOUT pins.
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The bi-directional Processor data port provides the
processor interface to the device. On write cycles, all
devices respond in parallel. On read cycles, the appro-
priate device responds without additional intervention
from the processor.
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Processor port address bus. Selects which device register
is accessed. Bit 0 is only used when the port is set to 16-bit
mode, otherwise it should be held at a valid logic level.
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R/W is the processor port read/write control pin. This pin
is HIGH for reads, LOW for writes.
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/PCS is the processor port chip select pin. When LOW this
pin indicates a cycle to the processor port. On write cycles
data must be set up to the rising edge of /PCS. On read
cycles /PCS controls the output enable of the PROCD bus.
Note that /PCS may be asynchronous to CLK.
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When PROCREADY is HIGH, indicates the processor
read data is available or the processor write data is
accepted. Priority may be set between the DIN port and
the processor port. Note PROCREADY may be LOW for
up to 800 CLK periods after /RESET is taken HIGH. The
JTAG interface is able to set PROCREADY to HIGH-Z.
,17 2XWSXW
INT interrupt. Indicates the aged or learned queue has at
least one entry or a write exception occurred. The service
routine should either check the AQUEUE, LQUEUE, and
WEX registers, or bits 26–29 of the Address Index
register, to determine the cause. The interrupt is cleared
after the appropriate flag register has been read and will
not be reasserted until either the queue(s) are emptied and
then get at least one entry again, or another write exception
occurs. The JTAG interface is able to set INT to HIGH-Z.
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The /RESET input is used to reset the MUAA RCP.
/RESET must be asserted for at least 3 CLK periods.
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The rising edge of CLK input is the device clock.
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/FF is active when the device (or chain of devices) is full.
/FF becomes inactive when any one device has two open
entries. The JTAG interface is able to set /FF to HIGH-Z.
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When two or more devices are chained they communicate
among themselves using the CHAIN[3:0] signals. See
Chaining section. Internally Pulled-up.
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When two or more devices are chained they communicate
among themselves using the CHAINUP signals. See
Chaining section. The JTAG interface is able to set
CHAINUP to HIGH-Z.
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When two or more devices are chained they communicate
among themselves using the CHAINDN signals. See
Chaining section. The JTAG interface is able to set
CHAINDOWN to HIGH-Z.
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When two or more devices are chained they communicate
among themselves using the CHAINCS signals. See
Chaining section. Internally pulled up.
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