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參數(shù)資料
| 型號： | MUAA8K80-20QGC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 332K |
| 代理商： | MUAA8K80-20QGC |
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The MUSIC MUAA Routing Co-Processor (RCP) family
consists of 80-bit wide content-addressable memories
(CAMs), available in depths of 2K and 8K words. The
CAM/RAM associated data partition is programmable
from 32 bits of CAM and 48 bits of associated data, to 80
bits of CAM and 0 bits of RAM. The MUAA RCP can
perform normal routing functions such as search, insert,
and delete on single entries and can age multiple entries
simultaneously. In addition, there is a learn instruction,
particularly
useful
in
networking
applications.
For
maximum flexibility all the operations may be performed
either through the processor port or through the synchro-
nous port. Operations may occur on both ports simulta-
neously; the port with the highest priority will gain access
first if both ports require a read or write into the CAM
array simultaneously.
The synchronous interface consists of 32-bit wide input
and output ports, both of which may be configured as 16
bits. The data is multiplexed into and out of the CAM and
RAM associated data field. Where input or output data is
wider than the port, it is loaded or unloaded in multiple
cycles starting with the least significant word. Internally
the device is pipelined; once an operation is started on the
synchronous port the next operation may be loaded and the
results
of
the
previous
operation
unloaded,
thus
maximizing device throughput.
Multiple MUAA RCPs may be chained transparently to
provide deeper memory. No software configuration is
necessary. Each MUAA RCP detects where it is in the
chain from the chaining pins on the previous device. A
register is provided to inform the host of the total available
CAM memory and the number of CAMs chained. All
operations to the chained CAM are totally transparent. No
individual device selection or addressing is required.
The MUSIC MUAA RCP has aging, auto-aging, and
learning functions. All entries have a 9-bit time stamp and
may be marked as static to prevent the aging function from
deleting them. When auto aging is enabled it may be
configured to have higher or lower priority access than the
ports.
Two internal virtual queues of learned and aged entries are
available. As entries are learned or aged out they are
tagged as such and may be read from the device through
either of the ports. This feature enables simple host
management of aged out and learned entries.
IEEE Standard. 1149.1 (JTAG) testability is implemented
providing BYPASS, SAMPLE/PRELOAD, EXTEST,
CLAMP, and HIGH-Z functions.
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