參數(shù)資料
型號: MTV412MF128
廠商: Electronic Theatre Controls, Inc.
英文描述: 8051 Embedded Monitor Controller 128K Flash Type with ISP
中文描述: 8051嵌入式控制器的ISP監(jiān)控128K閃存式
文件頁數(shù): 15/26頁
文件大?。?/td> 255K
代理商: MTV412MF128
MYSON-CENTURY
TECHNOLOGY
MTV412M
(Rev 0.9)
HVCTR3
(w) : HSYNC clamp pulse control register.
CLPEG = 1
Clamp pulse follows HSYNC leading edge.
= 0
Clamp pulse follows HSYNC trailing edge.
CLPPO = 1
Positive polarity clamp pulse output.
= 0
Negative polarity clamp pulse output.
CLPW2 : CLPW0 : Pulse width of clamp pulse is
[(CLPW2:CLPW0) + 1] x 0.167
μ
s for 12MHz X’tal selection.
HVCTR4
(w) :
DF1, DF0 :
= 0,0
The digital filter will treat any HSYNC pulse shorter than one OSC period
(83.33ns) as noise, between one and two OSC period (83.33ns to 166.67ns) as
unknown region, and longer than two OSC period (166.67ns) as pulse.
= 0,1
The digital filter will treat any HSYNC pulse shorter than half OSC period
(41.66ns) as noise, between half and one OSC period (41.66ns to 83.33ns) as
unknown region, and longer than one OSC period (83.33ns) as pulse.
= 1,x
Disable the digital filter for HSYNC.
INTFLG
(w) : Interrupt flag. An interrupt event will set its individual flag, and, if the corresponding interrupt
enable bit is set, the INT1 source of 8051 core will be driven by a zero level. Software
MUST clear this register while serving the interrupt routine.
HPRchg= 1
No action.
= 0
Clears HSYNC presence change flag.
VPRchg= 1
No action.
= 0
Clears VSYNC presence change flag.
HPLchg = 1
No action.
= 0
Clears HSYNC polarity change flag.
VPLchg = 1
No action.
= 0
Clears VSYNC polarity change flag.
HFchg = 1
No action.
= 0
Clears HSYNC frequency change flag.
VFchg = 1
No action.
= 0
Clears VSYNC frequency change flag.
Vsync = 1
No action.
= 0
Clears VSYNC interrupt flag.
INTFLG
(r) :
Interrupt flag.
HPRchg= 1
Indicates a HSYNC presence change.
VPRchg= 1
Indicates a VSYNC presence change.
HPLchg = 1
Indicates a HSYNC polarity change.
VPLchg = 1
Indicates a VSYNC polarity change.
HFchg = 1
Indicates a HSYNC frequency change or counter overflow.
VFchg = 1
Indicates a VSYNC frequency change or counter overflow.
Vsync = 1
Indicates a VSYNC interrupt.
INTEN
(w) :
Interrupt enable.
EHPR = 1
Enables HSYNC presence change interrupt.
EVPR = 1
Enables VSYNC presence change interrupt.
EHPL = 1
Enables HSYNC polarity change interrupt.
EVPL = 1
Enables VSYNC polarity change interrupt.
EHF
= 1
Enables HSYNC frequency change / counter overflow interrupt.
Revision 0.9 - 15 - April 2002
VBpl
= 1
= 0
Negative polarity VBLANK output.
Positive polarity VBLANK output.
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