參數(shù)資料
型號: MTV412MF128
廠商: Electronic Theatre Controls, Inc.
英文描述: 8051 Embedded Monitor Controller 128K Flash Type with ISP
中文描述: 8051嵌入式控制器的ISP監(jiān)控128K閃存式
文件頁數(shù): 14/26頁
文件大小: 255K
代理商: MTV412MF128
MYSON-CENTURY
TECHNOLOGY
MTV412M
(Rev 0.9)
6.9 H/V SYNC Processor Register
Reg name
HVSTUS
F40h(r)
HCNTH
F41h(r)
HCNTL
F42h(r)
VCNTH
F43h(r)
VCNTL
F44h(r)
HVCTR0
F40h(w)
HVCTR2
F42h(w)
HVCTR3
F43h(w)
HVCTR4
F44h(w)
INTFLG
F48h(r/w) HPRchg VPRchg HPLchg VPLchg
INTEN
F49h(w)
EHPR
HVSTUS
(r) : The status of polarity, present and static level for HSYNC and VSYNC.
CVpre = 1
The extracted CVSYNC is present.
= 0
The extracted CVSYNC is not present.
Hpol
= 1
HSYNC input is positive polarity.
= 0
HSYNC input is negative polarity.
Vpol
= 1
VSYNC (CVSYNC) is positive polarity.
= 0
VSYNC (CVSYNC) is negative polarity.
Hpre
= 1
HSYNC input is present.
= 0
HSYNC input is not present.
Vpre
= 1
VSYNC input is present.
= 0
VSYNC input is not present.
Hoff*
= 1
Off level of HSYNC input is high.
= 0
Off level of HSYNC input is low.
Voff*
= 1
Off level of VSYNC input is high.
= 0
Off level of VSYNC input is low.
*Hoff and Voff are valid when Hpre=0 or Vpre=0.
HCNTH
(r) :
H-Freq counter's high bits.
Hovf
= 1
H-Freq counter is overflowed, this bit is cleared by H/W when condition removed.
HF13 - HF8 :
6 high bits of H-Freq counter.
HCNTL
(r) :
H-Freq counter's low byte.
VCNTH
(r) :
V-Freq counter's high bits.
Vovf
= 1
V-Freq counter is overflowed, this bit is cleared by H/W when condition removed.
VF11 - 8 :
4 high bits of V-Freq counter.
VCNTL
(r) :
V-Freq counter's low byte.
HVCTR0
(w) : H/V SYNC processor control register 0.
C1, C0 = 1,1
Selects CVSYNC as the polarity, freq and VBLANK source.
= 1,0
Selects VSYNC as the polarity, freq and VBLANK source.
= 0,0
Disables composite function.
= 0,1
H/W automatically switches to CVSYNC when CVpre=1 and VSpre=0.
NoHins = 1
HBLANK has no insert pulse in composite mode.
= 0
HBLANK has insert pulse in composite mode.
HBpl = 1
Negative polarity HBLANK output.
= 0
Positive polarity HBLANK output.
Revision 0.9 - 14 - April 2002
addr
bit7
CVpre
Hovf
HF7
Vovf
VF7
C1
bit6
HF6
VF6
C0
CLPEG CLPPO CLPW2 CLPW1 CLPW0
bit5
Hpol
HF13
HF5
VF5
NoHins
bit4
Vpol
HF12
HF4
VF4
bit3
Hpre
HF11
HF3
VF11
VF3
bit2
Vpre
HF10
HF2
VF10
VF2
bit1
Hoff
HF9
HF1
VF9
VF1
HBpl
DF1
bit0
Voff
HF8
HF0
VF8
VF0
VBpl
DF0
Vsync
EVsync
HFchg
EHF
VFchg
EVF
EVPR
EHPL
EVPL
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