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參數(shù)資料
| 型號： | MTV012A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8051 Embedded CRT Monitor Controller Mask Version |
| 中文描述： | CRT顯示器8051嵌入式控制器掩模版 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 102K |
| 代理商： | MTV012A |
MYSON
TECHNOLOGY
MTV012A
MTV012A Revision 1.1 12/23/1998
12/14
EMI
= 1
→
Enables master IIC bus interrupt.
MBUF
(w) :
Master IIC data shift register write; after START and before STOP condition, this
register will resume MTV012A's transmission to the IIC bus.
MBUF
(r) :
Master IIC data shift register read; after START and before STOP condition, this
register will resume MTV012A's receiving from the IIC bus.
WDT
(w) :
Watchdog timer control register.
= 1
= 1
CLRDDC
= 1
LVSEL
= 1
= 0
WDT2: WDT0
= 0
= 1
= 2
= 3
= 4
= 5
= 6
= 7
WEN
WCLR
→
Enables the watchdog timer.
→
Clears the watchdog timer.
→
Clears the DDC2 flag.
→
Low voltage reset will occur when VDD < 4.1V.
→
Low voltage reset will occur when VDD < 3.6V.
→
Overflow interval = 8 x 0.25 sec.
→
Overflow interval = 1 x 0.25 sec.
→
Overflow interval = 2 x 0.25 sec.
→
Overflow interval = 3 x 0.25 sec.
→
Overflow interval = 4 x 0.25 sec.
→
Overflow interval = 5 x 0.25 sec.
→
Overflow interval = 6 x 0.25 sec.
→
Overflow interval = 7 x 0.25 sec.
FIFO
(w) :
Writes FIFO contents.
SLVCTR
(w) :
Slave IIC block control.
= 1
= 0
= 1
= 0
= 1
ESLVMI
ENSLV
→
Enables slave IIC block.
→
Disables slave IIC block.
→
Slave IIC connects to ISDA/ISCL.
→
Slave IIC connects to HSDA/HSCL.
→
Enables slave buffer interrupt.
→
Enables slave address match interrupt.
SLVsel
ESLVBI
= 1
SLVSTUS
(r) : Slave IIC block status.
WADR
SLVS
= 1
= 1
→
The data in SLVBUF is a word address.
→
The slave block has detected a START; will be cleared when STOP
is detected.
→
SLVBUF has been loaded with a new data byte; reset by S/W
reading SLVBUF.
→
Slave block has detected the slave address match condition; cleared
by S/W writing 0 to SLVMI.
SLVBI
= 1
SLVMI
= 1
SLVINT
(w) :
Slave block interrupt. The SLVBI/SLVMI interrupt will set its flag, and, if the
corresponding interrupt enable bit is set, the 8051 INT1 source will be driven by a zero
level. Software MUST clear this register while serving the interrupt routine.
= 1
→
No action.
= 0
→
Clears SLVMI.
SLVMI
SLVBUF
(r) :
Slave IIC data latch.
SLVADR
(w) : Slave IIC address to which the slave block should respond.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MTV012E | 8051 Embedded CRT Monitor Controller OTP Version |
| MTV018 | IC TXRX PHY 10/100 3.3V 48LQFP |
| MTV021 | Enhanced Super On-Screen Display |
| MTV021N20 | Enhanced Super On-Screen Display |
| MTV021N24 | Enhanced Super On-Screen Display |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MTV012E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8051 Embedded CRT Monitor Controller OTP Version |
| MTV016 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced On-Screen-Display Controller |
| MTV016N-10 | 制造商:Myson Century Inc 功能描述:IC, PDIP16 |
| MTV016N-18 | 制造商:Myson Century Inc 功能描述:IC, PDIP16 |
| MTV018 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Super On-Screen-Display |
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