MYSON
TECHNOLOGY
MTV003N
(MTV003)
MTV003 Revision 2.3 07/01/1998
4/13
for each converter by setting the corresponding register.
3.3 SYNC Processor
The sync processor contains the following functions: polarity detection, presence detection, H-Freq counter,
V-Freq counter and sync signal separation for input SYNC sources (HS and VS). It can be programmed to
change the detected polarity status and output polarity of SYNC pins (HBLANK and VBLANK) by using the
command interface. The timing diagrams of sync processing are shown as Fig. 2 in section 8.0. The internal
SYNC signals (Hsync and Vsync) are extracted from different sources according to the following modes of
operation.
Mode
VS
HS
Comment
1
2
3
4
Separate(H+V)
Composite(H/V)
Suspend
Off
present
not present
present
not present
present
present
not present
not present
HS = H or H/V sync
HS= H/V sync
-
-
3.4 H-Freq Table
After the "start H-Freq count" command is issued over 10 ms (for 15.7KHz) and HCFF(H-Freq Count Finished
Flag) is set
High,
the H-Freq output (HF9 - HF0) is valid. The output value of H-Freq is calculated using the
following formula:
output value = [(1/fHfreq(KHz)) x 64 x 4000] / 16
H-Freq(KHz)
15.7
18.7
21.8
30
31.5
33.5
35.5
36.8
38
40
48
50
57
60
64
100
Output value hexadecimal 11 bits decimal
3FB
357
2DD
215
1FB
1DD
1C2
1B2
1A5
190
14D
140
118
10A
0FA
0A0
Tolerance (%)
0.0981354
0.1169591
0.1364256
0.1876172
0.1972386
0.2096436
0.2222222
0.2304147
0.2375297
0.2500000
0.3003003
0.3125000
0.3571428
0.3759398
0.4000000
0.6250000
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1019
855
733
533
507
477
450
434
421
400
333
320
280
266
250
160
3.5 V-Freq Table
After the "start V-Freq count" command is issued over 120 ms (for 50HZ) and VCFF (V-Freq Count Finish Flag)
is set
High,
the V-Freq output (VF8 - VF0) is valid. The output value of V-Freq is calculated according to the
following formula:
output value = [(4/fVfreq(Hz)) x 4000000] / (64 x 16)