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參數(shù)資料
| 型號： | MTP805S |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8051 Embedded USB/PS2 Keyboard/Mouse Controller |
| 中文描述： | 8051嵌入式USB/PS2鍵盤/鼠標(biāo)控制器 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 125K |
| 代理商： | MTP805S |
MYSON
TECHNOLOGY
MTP805
(Rev. 0.9)
Revision 0.9 - 11 - 2000/07/19
RsmIE = 1
KbdIE = 1
MsIE
→
Enable RsmI interrupt.
→
Enable KbdI interrupt.
→
Enable MsI interrupt.
= 1
USBCTR
(r/w) : USB control register.
Susp
= 1
RsmO = 1
EP1cfgd = 1
EP2cfgd = 1
RC0rdy = 1
= 0
→
S/W force USB interface into suspend mode.
→
S/W force USB interface send RESUME signal in suspend mode.
→
Endpoint 1 is configed.
→
Endpoint 2 is configed.
→
Enable the Endpoint 0 to respond to OUT token.
→
Endpoint 0 will respond NAK to OUT token.
This bit can be set or cleared by S/W, clear by H/W while RC0I occurs.
→
MTP805 will stall an invalid OUT token during Control Read transfer.
CtrRD = 1
EP0STUS
(r) : Endpoint 0 status.
RC0tgl = 1
= 0
RC0err = 1
= 0
EP0dir = 1
= 0
EP0set = 1
= 0
RC0cnt :
→
Receive a DATA1 packet.
→
Receive a DATA0 packet.
→
Receive DATA packet error.
→
Receive DATA packet good.
→
Last transfer is transmit direction (IN).
→
Last transfer is receive direction (OUT, SETUP).
→
Last transfer is a SETUP.
→
Last transfer is not a SETUP.
Last transfer's receive byte count.
TX0CTR
(r/w) : Endpoint 0 transmit control register.
TX0rdy = 1
→
Enable the Endpoint 0 to respond to IN token.
= 0
→
Endpoint 0 will respond NAK to IN token.
This bit can be set or cleared by S/W, clear by H/W while Host ack the transfer.
TX0tgl = 1
→
Endpoint 0 will transmit DATA1 packet.
= 0
→
Endpoint 0 will transmit DATA0 packet.
EP0stall = 1
→
Endpoint 0 will stall OUT/IN packet.
TX0cnt (w) :
Endpoint 0 transmit byte count, write only.
TX1CTR
(r/w) : Endpoint 1 transmit control register.
TX1rdy = 1
→
Enable the Endpoint 1 to respond to IN token.
= 0
→
Endpoint 1 will respond NAK to IN token.
This bit can be set or cleared by S/W, clear by H/W while Host ack the transfer.
TX1tgl = 1
→
Endpoint 1 will transmit DATA1 packet.
= 0
→
Endpoint 1 will transmit DATA0 packet.
EP1stall = 1
→
Endpoint 1 will stall IN packet.
TX1cnt (w) :
Endpoint 1 transmit byte count, write only.
TX2CTR
(r/w) : Endpoint 1 transmit control register.
TX2rdy = 1
→
Enable the Endpoint 2 to respond to IN token.
= 0
→
Endpoint 2 will respond NAK to IN token.
This bit can be set or cleared by S/W, clear by H/W while Host ack the transfer.
TX2tgl = 1
→
Endpoint 2 will transmit DATA1 packet.
= 0
→
Endpoint 2 will transmit DATA0 packet.
EP2stall = 1
→
Endpoint 2 will stall IN packet.
TX2cnt (w) :
Endpoint 1 transmit byte count, write only.
KSI
(r) :
KSI7~0’s read result.
LED
(w) :
Data load into the GPO0 / LED2~0 output latch.
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