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參數(shù)資料
| 型號： | MTD1P40E |
| 廠商： | MOTOROLA INC |
| 元件分類： | JFETs |
| 英文描述： | 1 A, 400 V, 8 ohm, P-CHANNEL, Si, POWER, MOSFET |
| 封裝： | DPAK-3 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 182K |
| 代理商： | MTD1P40E |
MTD1P40E
5
Motorola TMOS Power MOSFET Transistor Device Data
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
Qg, TOTAL GATE CHARGE (nC)
12
8
6
4
2
0
03
6
9
12
V
DS
,DRAIN–T
O–SOURCE
VOL
TAGE
(VOL
TS)
V
GS
,GA
TE–T
O–SOURCE
VOL
TAGE
(VOL
TS)
400
300
200
100
0
TJ = 25°C
ID = 1.0 A
QT
Q2
Q3
VGS
t,TIME
(ns)
100
10
1
10
100
RG, GATE RESISTANCE (OHMS)
TJ = 25°C
ID = 1.0 A
VDD = 200 V
VGS = 10 V
td(off)
td(on)
tf
tr
10
VDS
0
0.4
0.8
0
0.1
0.2
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
I S
,SOURCE
CURRENT
(AMPS)
VGS = 0 V
TJ = 25°C
1.2
2.4
1.0
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
Figure 10. Diode Forward Voltage versus Current
15
500
600
Q1
1.6
2.0
0.3
0.4
0.5
0.6
0.7
0.8
0.9
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the
maximum simultaneous drain–to–source voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction
temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”
Switching between the off–state and the on–state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the transition
time (tr,tf) do not exceed 10 s. In addition the total power av-
eraged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(R
θJC).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E–FETs can withstand the stress of
drain–to–source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
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