參數資料
型號: MTC20454-TQ-I
廠商: 意法半導體
英文描述: QUAD INTEGRATED ADSL CMOS ANALOG FRONT END CIRCUIT
中文描述: 四集成ADSL模擬前端的CMOS電路
文件頁數: 12/15頁
文件大?。?/td> 513K
代理商: MTC20454-TQ-I
MTC20454
12/15
Receive / Transmit Interface Timing
This interface is a triple (RX,TX, TXE) nibble-serial interface running at 8.8 MHz sampling (normal mode).
The data are represented in 16 bits format, and transferred in groups of 4 bits (nibbles). The LSBs are
transferred first. The MTC20454 generates a nibble clock (= master clock in normal mode, CLKNIB in
OSR = 2 mode) and word signals shared by the three interfaces.
Data is transmitted on the rising edge of the master clock (CLKM/CLKNIB) and sampled on the low going
edge of CLKM/CLKNIB. This holds for the data stream from MTC20454 and rom the digital processor. Da-
ta,
CLWD set-up and hold times are 5 ns with reference to the falling edge of CLKM/CLKNIB. RXD is sampled
with CLKM rising edge.
Figure 8. TX/RX Digital Interface Timing
Table 5. TX/RX Digital Interface timing
Reset Function
The MTC20454 is placed in reset mode when the RESETN pin is pulled to ground (active low signal). The
chip status is depicted in the following table:
Symbol
Parameter
Min
Typ
Max
Ts
Setup time
0.5 ns
-
-
Th
Hold time
0.2 ns
-
-
Tdv
Data valid
0.5 ns
-
4 ns
Reset
CLKM pin is replicating the CLKIN input clock. System clock available
CLKWD is not generated. The pin stays at high level
Digital blocks are in reset: no activity
Analog blocks are in powerdown
External driver is forced to powerdown
TXDx
N0
Tdv
N1
N2
N3
RXDx
CLKM
35.328Mhz
CLKWD
8.832Mhz
Th
Tdv
Ts
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參數描述
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MTC20455 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:QUAD ADSL DMT TRANSCEIVER
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MTC20455-MB-I1 功能描述:射頻收發(fā)器 ADSL DMT Transceiver RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數據速率:2000 Kbps 調制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray