參數(shù)資料
型號(hào): MTC20454-TQ-I
廠商: 意法半導(dǎo)體
英文描述: QUAD INTEGRATED ADSL CMOS ANALOG FRONT END CIRCUIT
中文描述: 四集成ADSL模擬前端的CMOS電路
文件頁(yè)數(shù): 10/15頁(yè)
文件大?。?/td> 513K
代理商: MTC20454-TQ-I
MTC20454
10/15
DIGITAL INTERFACE
Control Interface
The digital code setting for the MTC20454 configuration is sent over a serial line (CTRLIN) using the word
clock (CLWD). The data burst is composed of 16 bits from which the first bit is used as start bit (‘0’), the
three LSBs being used to identify the data contained in the 12 remaining bits. Test related data are latched
but they are overruled by the normal settings if the TEST pin is low.
Control Interface Timing
The control interface bits are considered valid on each positive edge of the master clock (CLKM). They
will be sampled at this moment. The stop bit will trigger the internal data validation.
The timing requirements are depicted in the following figure and table:
Table 1. Control interface timing requirements
Figure 7. Control interface chronodiagram
Symbol
Parameter
Min
Typ
Max
Remarks
Ts
Setup time
0.5 ns
-
-
Th
Hold time
0.2 ns
-
-
Tdv
Data valid
0.5 ns
-
4 ns
CTRLIN
Start
bit
ctrl cmd
bits
Ts
Th
Tdv
CLKM
CLKWD
1 stop
bit (high)
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