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參數(shù)資料
| 型號： | MT933 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 3.3V 10/100 Fast Ethernet Transceiver to MII |
| 中文描述： | 3.3 10/100快速以太網(wǎng)收發(fā)器，以信息產(chǎn)業(yè)部 |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 360K |
| 代理商： | MT933 |
8
MT933
Pin list
Pin #
Name
Type
Description
MD interface
20
RXIN
Input
Differential receive pair from magnetics (-)
19
RXIP
Input
Differential receive pair from magnetics (+)
28
TXON
Output
100 Differential transmit pair to magnetics (-)
23
TXOP
Output
100 Differential transmit pair to magnetics (+)
35
TXREF10
Input
10BASE-T transmitter current setting pin
36
TXREF100
Input
100BASE-TX transmitter current setting pin
14
RESETN
IOput
Active low, power on reset output and external reset input
41
XTAL1
Input
25MHz crystal input
40
XTAL2
Input
25MHz crystal input
MII interface
46
MDC
Input
Management interface clock (up to 2.5MHz)
45
MDIO
IOput
Management data
53
RX_CLK
Output
Receive clock (2.5MHz for 10, 25MHz for 100)
55, 56, 57, 58 RXD0, RXD1,
Output
Receive data MII interace
RXD2, RXD3
51
RX_DV
Output
Receive data valid. Active high.
59
RX_ER
Output
Receive error. Active high. (RXD4 in symbol mode)
43
REFCLK
Input
Reference clock
64
TX_CLK
Output
Transmit clock (2.5MHz for 10, 25MHz for 100)
60, 61, 62, 63 TXD0, TXD1,
Input
Transmit Data MII interface
TXD2, TXD3
4
TX_EN
Input
Transmit Enable. Active high.
2
TX_ER
Input
Transmit Error. Active high. (TXD4 in symbol mode)
50
CRS
Output
Carrier sense signal. Active high.
49
COL
Output
Collision signal. Active high.
22
ANEN
Input
Auto Negotiation enable. Active high.
48
MINT
Output
MII interrupt control.
6
ACTST
Output
Receive / transmit active indication (LED interface). Active low.
7
COLST
Output
Collision active indication (LED interface) Active low.
11
FDST
IOput
Full duplex indication when RESET_N high (LED interface). Active low. Input
when RESET_N is low. High input means 933 advertises full duplex capability.
Output
Link OK indication (LED interface). Active low.
5
LNKST
12
SPDST
IOput
Speed indication when RESET_N high (LED interface). High for 100Mb/s mode.
Input when RESET_N is low. Low input means 933 advertises 100Mb/s
capability.
31, 30, 29,
17, 13
PA0, PA1,
PA2, PA3, PA4
Input
Phy address
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