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參數資料
| 型號： | MT9092 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Digital Telephone with HDLC(數字電話（帶高階數據鏈路控制HDLC）) |
| 中文描述： | 數字電話（數字電話（帶高階數據鏈路控制的HDLC）與的HDLC） |
| 文件頁數： | 22/44頁 |
| 文件大小： | 278K |
| 代理商： | MT9092 |
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MT9092
7-24
Note: Bits marked "-" are reserved bits and should be written with logic "0".
Intsel
When high, this bit will cause bit 2 of the Interrupt Register to reflect a Transmit FIFO underrun (Txunder). When low, this
interrupt will reflect a frame abort (FA).
When high, this bit will inhibit transmission of the CRC. That is, the transmitter will not insert the computed CRC onto the bit
stream after seeing the EOP tag byte. The microprocessor then has the opportunity to insert the CRC as part of the data
field.
When high, this bit will enable seven bits of address recognition in the first address byte. The received address byte must
have bit 0 equal to 1 which indicates a single address byte is being received.
When high, this bit will change the Rx FIFO interrupt and status level from 15 to 5 bytes, thus allowing the microprocessor
more time to react to interrupt conditions.
When high, this bit will change the Tx FIFO interrupt and status level from 4 to14 bytes, thus allowing the microprocessor
more time to react to interrupt conditions.
When high, the Rx FIFO will be reset. This causes the receiver to be disabled until the next reception of a flag, an
occurrence which resets this bit. The Status Register will identify the FIFO as being empty. However, the actual bit values
of data in the Rx FIFO will not be reset.
When high, the Tx FIFO will be reset. The Status Register will identify the FIFO as being empty. This bit will be reset when
data is written to the Tx FIFO. The actual bit values of data in the Tx FIFO will not be reset..
Tcrci
Seven
Flrx
Fltx
Rxfrst
Txfrst
HDLC Control Register 2
ADDRESS = 05h WRITE/READ VERIFY
Power Reset Value
0000 0000
7
6
5
4
3
2
1
0
Intsel
-
Tcrci
Seven
Rxfrst
Txfrst
Flrx
Fltx
This register is used with the Interrupt Register to mask out the interrupts that are not required by the microprocessor. Interrupts that
are masked out will not produce an IRQ; however, they will set the appropriate bit in the Interrupt Register. An interrupt is disabled
when the microprocessor writes a 0 to a bit in this register. This register is cleared on power reset.
HDLC Interrupt Enable Register
ADDRESS = 06h WRITE/READ VERIFY
Power Reset Value
0000 0000
7
6
5
4
3
2
1
0
GA
EOPD TEOP EOPR
TxFL
FA/Tx
Under
RxFf
Rx
Ovfl
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|---|---|
| MT9092 | ISO2-CMOS ST-BUS⑩ FAMILY Digital Telephone with HDLC (HPhone-II) |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MT9092AP | 制造商:Microsemi Corporation 功能描述: |
| MT9092AP1 | 制造商:Zarlink Semiconductor Inc 功能描述:DGTL TEL 44PLCC - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE H-PHONE-PLUS PLCC |
| MT9092APR | 制造商:Microsemi Corporation 功能描述:DGTL TEL 44PLCC - Tape and Reel |
| MT9092APR1 | 制造商:Microsemi Corporation 功能描述:DGTL TEL 44PLCC - Tape and Reel 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL TELEPHONE CIRCUIT 44PLCC 制造商:Microsemi Corporation 功能描述:IC DGTL TELEPHONE CIRCUIT 44PLCC |
| MT9094 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO2-CMOS ST-BUS⑩ FAMILY Digital Telephone (DPhone-II) |
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