參數(shù)資料
型號(hào): MT9092
廠商: Mitel Networks Corporation
英文描述: Digital Telephone with HDLC(數(shù)字電話(帶高階數(shù)據(jù)鏈路控制HDLC))
中文描述: 數(shù)字電話(數(shù)字電話(帶高階數(shù)據(jù)鏈路控制的HDLC)與的HDLC)
文件頁(yè)數(shù): 18/44頁(yè)
文件大小: 278K
代理商: MT9092
MT9092
7-20
New Call Tone
The New Call Tone Generator produces a frequency
shifted square-wave used to toggle the speaker
driver outputs. This is intended for use where a
ringing signal is required concurrently with an
already established voice conversation in the
handset.
Programming of the DSP for New Call generator is
exactly as is done for the tone ringer micro-program
except that the OPT bit (DSP Control Register,
address 1Eh) is set high. In this mode the DSP does
not produce a frequency shifted squarewave output
to the filter CODEC section. Instead the DSP uses
the contents of the tone coefficient registers, along
with the tone warble rate register, to produce a gated
squarewave control signal output which toggles
between the programmed frequencies. This control
signal is routed to the New Call Tone block when the
NCT EN control bit is set (General Control Register,
address 0Fh). NCT EN also enables a separate gain
control block, for controlling the loudness of the
generated ringing signal. With the gain control block
set to 0dB the output is at maximum or 6 volts p-p.
Attenuation of the applied signal, in three steps of 8
dB, provide the four settings for New Call tone (0, -8,
-16, -24 dB). The NCT gain bits (NCTG
0
-NCTG
1
)
reside in the FCODEC Gain Control Register 2
(address 0Bh).
Watchdog
To maintain program integrity an on-chip watchdog
timer
is
provided
for
microcontroller reset pin. The watchdog output WD
(pin 17) goes high while the HPhone-
II
is held in
reset via the PWRST (pin 6). Release of PWRST will
cause WD to return low immediately and will also
start the watchdog timer. The watchdog timer is
clocked on the falling edge of F0i and requires only
this input, along with V
DD
, for operation.
connection
to
the
If the watchdog reset word is written to the watchdog
register (address 11h) after PWRST is released, but
before the timeout period (T=512mSec) expires, a
reset of the timer results and WD will remain low.
Thereafter, if the reset word is loaded correctly at
intervals less than 'T' then WD will continue low. The
first break from this routine, in which the watchdog
register is not written to within the correct interval or
it is written to with incorrect data, will result in a high
going WD output after the current interval 'T' expires.
WD will then toggle at this rate until the watchdog
register is again written to correctly.
5-BIT WATCHDOG RESET WORD
x=don’t care
Test Loops
Detail LBio and LBoi Loopback Register (address
16h)
LBio
Setting this bit causes data on DSTi to be
looped back to DSTo directly at the pins. The
appropriate channel enables Ch
0
EN -Ch
3
EN
must also be set.
LBoi
Setting this bit causes data on DSTo to be
looped back to DSTi directly at the pins.
W4
W3
W2
W1
W0
X
X
X
0
1
0
1
0
相關(guān)PDF資料
PDF描述
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