參數(shù)資料
型號(hào): MT90840AL
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Distributed Hyperchannel Switch
中文描述: TELECOM, DIGITAL TIME SWITCH, PQFP100
封裝: 14 X 20 MM, 2.80 MM HEIGHT, MO-112CC-1, MQFP-100
文件頁(yè)數(shù): 31/51頁(yè)
文件大小: 512K
代理商: MT90840AL
Data Sheet
MT90840
2-261
Applications
Distributed Isochronous Network
Low latency isochronous backbones provide for the
deployment of systems that require cost effective
implementation, high bandwidth, predictable data
transfer delays and direct synchronization with the
wide area network.
Some
Integration (CTI) require a large amount of
bandwidth to be transported between multiple
chassis within the same location, or between
separate locations. The MT90840 is ideal for
implementing physically distributed transport and
switching systems for multi-chassis or inter-shelf
communications.
applications
in
Computer
Telephony
The MT90840 bridges existing Zarlink ST-BUS
components into a new networking environment
where mixed data, voice and video signals can be
time-interchanged or multiplexed from serial PCM
streams
onto
serial
high-speed
multiplex (TDM) isochronous backbones operating at
time-division-
SONET rates such as 51 (STS-1) or 155 Mbps
(STS-3).
Today, transmission links operating at SONET rates
utilize
serial-to-parallel
converters (or framers) which perform embedded
framing functions and give the user access to the
payload of the high speed frame. The MT90840
provides an 8-bit bidirectional parallel data port
which directly interfaces to a high-speed framer
parallel data interface, allowing designers to build
distributed networking systems with interconnection
speeds up to 155 Mbps. Figure 16 shows an
example of a distributed networking application in a
CTI system.
and
parallel-to-serial
The MT90840's clock synchronization and reference
options allow many applications and topologies
when isochronous TDM backbones are required.
Two major clock synchronization schemes provided
by the MT90840 allow the serial port interface
(ST-BUS) to provide the master clock and frame
reference signals for the distributed high speed
backbone (master operation) or to derive the entire
ST-BUS clock and frame reference signals from the
high speed backbone (slave operation). This type of
Figure 16 - CTI Distributed Architecture Implemented with the MT90840
MT8977/9079
T1 & E1 I/F
Call
Processing
ST-BUS
MT896x
Filter/Codec
ST-BUS
ISO Ethernet
MUX
ST-BUS
LAN ADAPTER CARD
PSTN
24/30B+D
CTI
SERVER
CTI
SERVER
Up to 2400 TDM
channels of user data
Interchassis Signalling
(e.g. Zarlink’s Connection
Master Software)
CTI Server
Switching
BUS
e.g.; MVIP
155 Mbps
Framing &
Optics
MT90810
FMIC
MT90840
MT90810
FMIC
MT8985/6
EDX
Filter/Codec
MT8930 / 71
(2B+D) I/F
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MT9085 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS PAC - Parallel Access Circuit