- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄383645 > MT9076AB (Mitel Networks Corporation) T1/E1/J1 3.3V Single Chip Transceiver PDF資料下載
參數(shù)資料
| 型號(hào)： | MT9076AB |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | T1/E1/J1 3.3V Single Chip Transceiver |
| 中文描述： | T1/E1/J1收發(fā)3.3V的單芯片收發(fā)器 |
| 文件頁(yè)數(shù)： | 54/160頁(yè) |
| 文件大?。?/td> | 416K |
| 代理商： | MT9076AB |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)當(dāng)前第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)
MT9076
Preliminary Information
50
There is one interrupt associated with the Out of Frame counter. A counter overflow interrupt may be enabled
by setting control bit OOFO high - bit 5 of Interrupt Mask Word Two (page 1H, address 1DH).
13.2.3
This eight bit counter MFOOF7 - MFOOF0 is located on page 4 address 15H, and is incremented once per
multiframe (1.5 ms for D4 and 3 ms for ESF) during the time that the framer is out of terminal frame
synchronization.
Multiframes out of Sync Counter (MFOOF7-MFOOF0)
There is a maskable interrupt associated with the measurement. A counter overflow interrupt may be enabled
by setting control bit MFOOFO high - bit 1 of Interrupt Mask Word Two (page 1H, address 1DH).
13.2.4
CRC-6 errors are recorded by this counter for ESF links. This 16 bit counter is located on page 4, addresses
18H and 19H.
CRC-6 Error Counter (CC15-0)
There are two maskable interrupts associated with the CRC error measurement. A single error may generate
an interrupt (enable by setting CRCI high - bit 6 of the Interrupt Mask Word One, page 1H, address 1CH). A
counter overflow interrupt may be enabled by setting control bit CRCO high - bit 6 of Interrupt Mask Word Two
(page 1H, address 1DH).
13.2.5
If the control bit EXZ (page 1 address 12H bit 5) is set low, the line code violation error counter will count
bipolar violations that are not part of B8ZS encoding. If the control bit EXZ (page 1 address 12H bit 5) is set
high, the line code violation error counter will count both bipolar violations that are not part of B8ZS encoding
and each occurance of excess zeros (more than 7 successive zeros in a received B8ZS encoded data stream
and more than 15 successive zeros in a non-B8ZS encoded stream). This counter LCV15-LCV0 is 16 bits long
(page 4H, addresses 16H and 17H) and is incremented once for every line code violation received. It should be
noted that when presetting or clearing the LCV error counter, the least significant LCV counter address should
be written to before the most significant location. This counter will suspend operation when terminal frame
synchronization is lost if the control bit OOFP is set (bit 2, address 1AH - Reset Control Word).
Line Code Violation Error Counter (LCV15-LCV0)
There are two maskable interrupts associated with the line code violation error measurement. A single error
may generate an interrupt (enable by setting LCVI high - bit 3 of the Interrupt Mask Word One, page 1H,
address 1CH). A counter overflow interrupt may be enabled by setting control bit LCVO high - bit 3 of Interrupt
Mask Word Two (page 1H, address 1DH).
13.2.6
There are two 8 bit counters associated with PRBS comparison; one for errors and one for time. Any errors that
are detected in the receive PRBS will increment the PRBS Error Rate Counter of page 04H, address 10H.
Writes to this counter will clear an 8 bit counter, PSM7-0 (page 01H, address 11H) which counts receive CRC
multiframes. A maskable PRBS counter overflow (PRBSO) interrupt (page 1, address 1DH) is associated with
this counter.
PRBS Error Counter (PS7-0)
13.2.7
This eight bit counter counts receive CRC multiframes. It can be directly loaded via the microport. The counter
will also be automatically cleared in the event that the PRBS error counter is written to by the microport. This
counter is located on page 04H, address 11H.
CRC Multiframe Counter for PRBS (PSM7-0)
13.3
E1 Counters
13.4
Errored FAS Counter (EFAS7-EFAS0)
An eight bit Frame Alignment Signal Error counter EFAS7 - EFAS0 is located on page 04H address 13H, and is
incremented once for every receive frame alignment signal that contains one or more errors.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9076 | T1/E1/J1 3.3V Single Chip Transceiver(T1/E1/J1 3.3V 單片收發(fā)器) |
| MT9079 | Advanced Controller for E1(先進(jìn)的E1幀調(diào)節(jié)器和控制器) |
| MT9080B | SMX - Switch Matrix Module(用于消費(fèi)類(lèi)轉(zhuǎn)換應(yīng)用的開(kāi)關(guān)矩陣模塊) |
| MT90810 | Flexible MVIP(Multi-Vendor Integration Protocol) Interface Circuit(彈性MVIP接口電路) |
| MT90812 | Integrated Digital Switch (IDX)(集成數(shù)字開(kāi)關(guān)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9076AP | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:T1/E1/J1 3.3V Single Chip Transceiver |
| MT9076B | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:T1/E1/J1 3.3 V Single Chip Transceiver |
| MT9076BB | 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 80LQFP - Trays |
| MT9076BB1 | 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 80LQFP - Trays |
| MT9076BP | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:T1/E1/J1 3.3 V Single Chip Transceiver |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。