
3
Advance Information
MT9045
11
F16o
Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output).
This is an 8kHz 61ns active low framing
pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS
operation at 8.192 Mb/s. See Figure 13.
12
F0o
Frame Pulse ST-BUS 2.048Mb/s (CMOS Output).
This is an 8kHz 244ns active low framing
pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS
operation at 2.048Mb/s and 4.096Mb/s. See Figure 13.
13
RSP
Receive Sync Pulse (CMOS Output).
This is an 8kHz 488ns active high framing pulse,
which marks the beginning of an ST-BUS frame. This is typically used for connection to the
Siemens MUNICH-32 device. See Figure 14.
14
TSP
Transmit Sync Pulse (CMOS Output).
This is an 8kHz 488ns active high framing pulse,
which marks the beginning of an ST-BUS frame. This is typically used for connection to the
Siemens MUNICH-32 device. See Figure 14.
15
F8o
Frame Pulse (CMOS Output).
This is an 8kHz 122ns active high framing pulse, which marks
the beginning of a frame. See Figure 13.
16
C1.5o
Clock 1.544MHz (CMOS Output).
This output is used in T1 applications.
18
LOCK
Lock Indicator (CMOS Output).
This output goes high when the PLL is frequency locked to
the input reference.
19
C2o
Clock 2.048MHz (CMOS Output).
This output is used for ST-BUS operation at 2.048Mb/s.
20
C4o
Clock 4.096MHz (CMOS Output).
This output is used for ST-BUS operation at 2.048Mb/s
and 4.096Mb/s.
21
C19o
Clock 19.44MHz (CMOS Output).
This output is used in OC3/STS3 applications.
22
FLOCK
Fast Lock Mode (Input).
Set high to allow the PLL to quickly lock to the input reference (less
than 500 ms locking time).
24
IC
Internal Connection.
Tie low for normal operation.
25
C8o
Clock 8.192MHz (CMOS Output).
This output is used for ST-BUS operation at 8.192Mb/s.
26
C16o
Clock 16.384MHz (CMOS Output).
This output is used for ST-BUS operation with a
16.384MHz clock.
27
C6o
Clock 6.312 Mhz (CMOS Output).
This output is used for DS2 applications.
29
HOLD
OVER
Holdover (CMOS Output).
This output goes to a logic high whenever the PLL goes into
holdover mode.
30
PCCi
Phase Continuity Control Input (Input).
The signal at this pin affects the state changes
between Primary Holdover Mode and Primary Normal Mode, and Primary Holdover Mode
and Secondary Normal Mode. The logic level at this input is gated in by the rising edge of
F8o. See Table 4.
32
NC
No connection.
Leave open circuit
33,34
IC
Internal Connection.
Tie low for normal operation.
36
MS2
Mode/Control Select 2 (Input).
This input determines the state (Normal, Holdover or
Freerun) of operation. The logic level at this input is gated in by the rising edge of F8o. See
Table 3.
37
MS1
Mode/Control Select 1 (Input).
F8o. See pin description for MS2. This pin is internally pulled down to VSS.
The logic level at this input is gated in by the rising edge of
Pin Description (continued)
Pin #
Name
Description