參數(shù)資料
型號(hào)： MT9042C
廠商： Mitel Networks Corporation
英文描述： Multitrunk System Synchronizer(多中繼系統(tǒng)同步裝置)
中文描述： Multitrunk系統(tǒng)同步器（多中繼系統(tǒng)同步裝置）
文件頁數(shù)： 4/28頁
文件大?。?/td> 126K
代理商： MT9042C
4
MT9042C
Functional Description
The MT9042C is a Multitrunk System Synchronizer,
providing timing (clock) and synchronization (frame)
signals to interface circuits for T1 and E1 Primary
Rate Digital Transmission links.
Figure 1 is a functional block diagram which is
described in the following sections.
Reference Select MUX Circuit
The MT9042C accepts two simultaneous reference
input signals and operates on their falling edges.
Either the primary reference (PRI) signal or the
secondary reference (SEC) signal can be selected
as input to the TIE Corrector Circuit. The selection is
based
on
the
Control,
Selection of the device. See Tables 1, 4 and 5.
Mode
and
Reference
Frequency Select MUX Circuit
The MT9042C operates with one of three possible
input reference frequencies (8kHz, 1.544MHz or
2.048MHz). The frequency select inputs (FS1 and
FS2) determine which of the three frequencies may
be used at the reference inputs (PRI and SEC). Both
inputs must have the same frequency applied to
them. A reset (RST) must be performed after every
frequency select input change. Operation with FS1
and FS2 both at logic low is reserved and must not
be used. See Table 1.
Time Interval Error (TIE) Corrector Circuit
The TIE corrector circuit, when enabled, prevents a
step change in phase on the input reference signals
(PRI or SEC) from causing a step change in phase at
the input of the DPLL block of Figure 1.
During reference input rearrangement, such as
during a switch from the primary reference (PRI) to
the secondary reference (SEC), a step change in
phase on the input signals will occur. A phase step
at the input of the DPLL will lead to unacceptable
phase changes in the output signal.
As shown in Figure 3, the TIE Corrector Circuit
receives one of the two reference (PRI or SEC)
signals, passes the signal through a programmable
delay line, and uses this delayed signal as an
internal virtual reference, which is input to the DPLL.
Therefore, the virtual reference is a delayed version
of the selected reference.
During a switch, from one reference to the other, the
State Machine first changes the mode of the device
FS2
FS1
Input Frequency
0
0
Reserved
0
1
8kHz
1
0
1.544MHz
1
1
2.048MHz
Table 1 - Input Frequency Selection
Figure 3 - TIE Corrector Circuit
Programmable
Delay Circuit
Control Signal
Delay Value
TRST
Resets Delay
Compare
Circuit
TIE Corrector
Enable
from
State Machine
Control
Circuit
Feedback
Signal from
Frequency
Select MUX
PRI or SEC
from
Reference
Select Mux
Virtual
Reference
to DPLL
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT9042CP 制造商:Microsemi Corporation 功能描述: 制造商:Mitel Networks Corporation 功能描述:
MT9042CP1 制造商:Microsemi Corporation 功能描述:SYNCHRONIZER 28PLCC - Rail/Tube 制造商:Microsemi Corporation 功能描述:PB FREE MULTITRUNK SYSTEM SYNCHRONIZER 制造商:Zarlink Semiconductor Inc 功能描述:SYNCHRONIZER 28PLCC - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE MULTITRUNK SYSTEM SYNCHRONIZER
MT9042CPR1 制造商:Microsemi Corporation 功能描述:SYNCHRONIZER 28PLCC - Tape and Reel 制造商:Zarlink Semiconductor Inc 功能描述:SYNCHRONIZER 28PLCC - Tape and Reel
MT9043 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 System Synchronizer
MT9043AN 制造商:Microsemi Corporation 功能描述:
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