參數(shù)資料
型號: MT90401
廠商: Mitel Networks Corporation
英文描述: SONET/SDH System Synchronizer(SONET/SDH 系統(tǒng)同步裝置(由一個數(shù)字鎖相環(huán)組成))
中文描述: 的SONET / SDH系統(tǒng)的同步器(SONET / SDH的系統(tǒng)同步裝置(由一個數(shù)字鎖相環(huán)組成))
文件頁數(shù): 5/9頁
文件大?。?/td> 110K
代理商: MT90401
MT90401
Pin Description (continued)
Product Brief
5
56
PCCi
Phase Continuity Control Input (3V Input).
The signal at this pin affects the state
changes between Primary Holdover Mode and Primary Normal Mode and Primary Holdover
Mode and Secondary Normal Mode. The logic level at this input is gated by the rising edge
of F8o.
57
LOCK
Lock Indicator (CMOS Output).
This output goes high when the PLL is in frequency lock to
the input reference.
58
FLOCK
Fast Lock Mode (Input).
In hardware mode, hold this pin high to lock 8 times faster than
normal to the input reference. This pin performs no function if the device is not in hardware
mode. In Fast Lock Mode, the wander generation of the PLL is, of necessity, compromised.
59
DS
Data Strobe (5V tolerant Input)
. This input is the active low data strobe of the Motorola
processor interface.
60
IC
Internal Connection.
Tie low for normal operation.
61
SECOOR
Secondary Reference Out Of Capture Range (CMOS Output).
A logic high at this pin
indicates that the secondary reference is off the PLL center frequency by more than 12
ppm. The calibration is done on a 1 second basis using a signal derived from the 20MHz
clock input on the C20i pin. When the accuracy of the 20MHz clock is
±
4.6ppm the effective
out of range limits of the SECOOR pin will be
±
1
6.6ppm.
Output Enable (Input)
. Tie high for normal operation. Tie low to force output clocks pins
F16, C16, C8, C4, C2, F0 to a high impedance state.
62
OE
63
CS
Chip Select (5V tolerant Input)
. This active low input enables the non-multiplexed
Motorola parallel microprocessor interface of the MT90401. When CS is set to high, the
microprocessor interface is idle and all bus I/O pins will be in a high impedance state.
64
RST
RESET (5V tolerant Input).
This active low input puts the MT90401 in a reset condition.
RST should be set to high for normal operation. The MT90401 should be reset after power-
up and after the selected reference frequency is changed. The RST pin must be held low for
a minimum of 1
μ
sec. to reset the device properly.
65
HW
Hardware Mode (Input)
. If this pin is tied low, the device is in microport mode and is
controlled via the microport. If it is tied high, the device is in hardware mode and is
controlled via the control pins MS1, MS2, FS1, FS2, FLOCK and SONET/SDH.
66-69
D0 - D3
Data 0 to Data 3 (5V tolerant Three-state I/O)
. These signals combined with D0,D1 and
D4-D7 form the bidirectional data bus of the parallel processor interface (D0 is the least
significant bit).
70
V
SS8
IC
Digital ground.
0 Volts.
71
Internal Connection.
Tie low for normal operation.
72
IC
Internal Connection.
Tie low for normal operation.
Positive Power Supply.
Digital supply (+3.3V
±
5%).
Data 4 to Data 7 (5V tolerant Three-state I/O).
These signals combined with D0-D3 form
the bidirectional data bus of the parallel processor interface (D7 is the most significant bit).
73
V
DD5
D4 - D7
74-77
78
R/W
Read/Write Strobe (5V tolerant Input).
In Motorola mode (R/W), this input controls the
direction of the data bus D[0:7] during a microprocessor access. When R/W is high, the
parallel processor is reading data from the MT90401. When low, the parallel processor is
writing data to the MT90401.
79
A0
Address 0 (5V tolerant Input).
Address and control input for the non-multiplexed parallel
processor interface. A0 is the least significant input.
80
IC
Internal Connection.
Tie low for normal operation.
Pin #
Name
Description
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