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MT90401
Pin Description (continued)
Product Brief
4
35
Tms
IEEE 1149.1a Test Mode Selection (Input)
. If not used, this pin should be pulled high.
36
Tclk
IEEE 1149.1a Test Clock Signal (Input)
. If not used, this pin should be pulled high.
37
Trst
IEEE 1149.1a Reset Signal (Input).
If not used, this pin should be held low.
38
Tdi
IEEE 1149.1a Test Data Input (Input).
If not used, this pin should be pulled high.
39
FS2
Frequency Select 2 (Input).
This input, in conjunction with FS1, selects which of four
possible frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be input to the PRI
and SEC inputs.
40
FS1
Frequency Select 1 (Input).
This input, in conjunction with FS2, selects which of four
possible frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be input to the PRI
and SEC inputs.
41
PRIOOR
Primary Reference Out Of Range (CMOS Output).
A logic high at this pin indicates that
the primary reference is off the PLL center frequency by more than 12 ppm. The calibration
is done on a 1 second basis using a signal derived from the 20MHz clock input on C20i.
When the accuracy of the 20MHz clock is
±
4.6ppm the effective out of range limits of the
PRIOOR pin will be
±
16.6
ppm.
Clock 1.544MHz (CMOS Output).
This output is used in T1 applications.
42
C1.5o
43
C6
Clock 6.312MHz (CMOS Output).
This output is used for DS2 or J2 applications.
44
IC
Internal Connection.
Tie low for normal operation
.
45
VSS
5
C19o
Digital ground.
0 Volts
46
Clock 19.44MHz (CMOS Output).
This output is used in OCN/STS-N and STM-N
applications.
47
RSEL
Reference Source Select (Input).
A logic low selects the PRI (primary) reference source
as the input reference signal and a logic high selects the SEC (secondary) input. The logic
level at this input is gated in by the rising edge of F8o.
48
TCLR
TIE Circuit Clear (Input).
A logic low at this input clears the Time Interval Error (TIE)
correction circuit resulting in a realignment of output phase with input phase. The TCLR pin
should be held low for a minimum of 300ns. When this pin is held low, the time interval error
correction circuit is disabled.
Positive Power Supply. Digital supply
(+3.3V
±
5%).
Digital ground.
0 Volts.
49
VDD
3
VSS
6
C20i
50
51
20 MHz Clock Input (5V tolerant Input).
This pin is the input for the master 20MHz clock.
52
V
SS7
C34/C44
Digital ground.
0Volts
53
Controlled Clock 34.368MHz / Clock 44.736MHz (CMOS Output).
This output clock is
programmable to be either 34.368MHz (for E3 applications) or 44.736MHz (for DS3
applications). The output clock is controlled via control pins in Hardware Mode or control
bits when the device is in Microport Mode.
If the E3DS3/OC3 control pin (in hardware mode) or if the E3DS3/OC3 control bit (in
microport mode) is high, the C34/C44 pin will output its nominal frequency. If the E3DS3/
OC3 control pin or control bit is low, the C34/C44 pin will output its nominal frequency
divided by 4. (C8.5o/C11o)
Positive Power Supply.
Digital supply (+3.3V
±
5%).
HOLDOVER
Holdover (CMOS Output).
This output goes high when the device is in holdover mode.
54
V
DD4
55
Pin #
Name
Description