參數(shù)資料
型號: MT8986AE
廠商: Mitel Networks Corporation
英文描述: CMOS ST-BUS⑩ FAMILY Multiple Rate Digital Switch
中文描述: 意法半導體的CMOS總線⑩家庭多速率數(shù)字開關
文件頁數(shù): 8/46頁
文件大小: 765K
代理商: MT8986AE
MT8986
Data Sheet
8
Zarlink Semiconductor Inc.
Identical Input/Output Data Rates
When identical input/output data rate is selected by the DMO bit, the I/O rate is determined by the IDR0-1 bits, and
the ODR0-1 bits are ignored. For each data rate specified by the IDR bits, different switching configurations can be
selected in the SCB1-0 bits.
Serial Links with Data Rates at 2.048 Mb/s
When 2.048 Mb/s data rate is selected at the IDR bits, four different I/O configurations can be selected by the
SCB1-0 bits (see Table 8); 8 x 8, 16 x 8, 4 x 4 with stream pair selection and nibble switching.
If 8 x 8 switching configuration is selected, a 256 x 256 channel non-blocking switching matrix is available. In this
configuration, the MT8986 device is configured with 8 input and 8 output data streams with 32 64 Kbit/s channels
each. The interface clock for this operation is 4.096 MHz with both ST-BUS and GCI compatibilities and the per-
channel selection between variable and constant throughput delay functions is provided. This configuration is
available in both the 40 and 44 pin packages.
In 16 x 8 switching configuration, a 512 x 256 channel blocking switch matrix is available. This configuration is only
provided in the 44 pin package and when the CPU interface is configured in multiplexed bus mode. The device
clock in this application is 4.096 MHz, ST-BUS or GCI compatible. This configuration only provides variable
throughput delay.
If the stream pair selection switching configuration is selected, only four input and four outputs (4 pairs of serial
streams) can be selected by the CPU to be internally connected to the switch matrix, totalling a 128 x 128 channel
non-blocking switch. From the 10 serial link pairs available, two pairs are permanently connected to the internal
matrix (STi0/STo0 and STi1/STo1). An internal stream pair selection capability allows two additional pairs of serial
links to be selected from the remaining 8 pairs (from STi/STo2 to STi9/STo9) and be connected to the internal matrix
along with the permanently connected STi0/STo0 and STi1/STo1 streams. The two additional pair of streams called
stream pair A and stream pair B, should be selected in the Stream Pair Selection register (SPS). The device clock
for this operation is 4.096 MHz compatible to ST-BUS and GCI interfaces. In addition, the per-channel selection
between variable or constant throughput delay is available. This configuration is only provided in the 44 pin
packages.
In case of nibble switching, 4-bit wide 32 kb/s data channels can be switched within the device. In this case, every
serial stream is run at 2.048 Mb/s and transports 64 nibbles per frame. When Nibble Switching is selected at SCB
bits, the MT8986 automatically assumes a 8 input x 4 output stream configuration, providing a blocking switch
matrix of 512 x 256 nibbles. If a non-blocking switch matrix is required for nibble switching, the switch capacity is
reduced to 256 x 256 channel with a 4 input x 4 output configuration; the non-blocking matrix can be arranged by
the user by selecting any four of the 8 input streams. In nibble switching the interface clock is 4.096 MHz.
Serial Links with Data Rates at 4.096 Mb/s
Two I/O configurations can be enabled by the SCB bits when input and output data rates are 4.096 Mb/s on each
serial stream: 8 x 4 and 4 x 4. When 8 x 4 switching configuration is selected, a 512 x 256 channel blocking switch
is available with serial streams carrying 64, 64 Kb/s channels each. For this operation, a 4.096 MHz interface clock
equal to the bit rate should be provided to MT8986. Only variable throughput delay mode is provided.
In case of 4 x 4 switching configuration, a 256 x 256 channel non-blocking switch is available with serial streams
carrying 64, 64 Kb/s channels each. In this configuration, the interface clock is 4.096 MHz and the per-channel
selection between variable and constant throughput delay operation is provided. Figure 20 shows the timing for
4.096 Mb/s operation.
Serial Links with Data Rates at 8.192 Mb/s
Only 2 input x 2 output stream configuration is available for 8.192 Mb/s, allowing a 256 x 256 channel non-blocking
switch matrix to be implemented. To enable this operation, the IDR bits should be programmed to select 8.192 Mb/s
rates and the SCB bits have no effect. At 8.192 Mb/s, every input and output stream provides 128 time-slots per
相關PDF資料
PDF描述
MT8986AL CMOS ST-BUS⑩ FAMILY Multiple Rate Digital Switch
MT8986AP CMOS ST-BUS⑩ FAMILY Multiple Rate Digital Switch
MT8D264G-6 x64 Fast Page Mode DRAM Module
MT8D264G-6X x64 EDO Page Mode DRAM Module
MT8D264G-7 x64 Fast Page Mode DRAM Module
相關代理商/技術參數(shù)
參數(shù)描述
MT8986AE1 制造商:Microsemi Corporation 功能描述:PB FREE MULTIPLE RATE DIGITAL SWITCH 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 256 X 256/512 X 256/128 X 128 131.072MBPS 5V 40P - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM/TSI SWITCH 512X256 40PDIP 制造商:Microsemi Corporation 功能描述:IC TDM/TSI SWITCH 512X256 40PDIP
MT8986AL 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 256 X 256/512 X 256/128 X 128 131.072MBPS 5V 44M - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 256 X 256/512 X 256/128 X 128 131.072MBPS 5V 44M - Trays
MT8986AL1 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 256 X 256/512 X 256/128 X 128 131.072MBPS 5V 44M - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 256 X 256/512 X 256/128 X 128 131.072MBPS 5V 44M - Trays
MT8986AP 制造商:Microsemi Corporation 功能描述:
MT8986AP1 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 256 X 256/512 X 256/128 X 128 131.072MBPS 5V 44P - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM/TSI SWITCH 512X256 44PLCC 制造商:Microsemi Corporation 功能描述:IC TDM/TSI SWITCH 512X256 44PLCC