參數(shù)資料
型號: MT8981DP1
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: ISO-CMOS ST-BUS
中文描述: TELECOM, DIGITAL TIME SWITCH, PQCC44
封裝: LEAD FREE, PLASTIC, MS-018AC, LCC-44
文件頁數(shù): 16/20頁
文件大小: 481K
代理商: MT8981DP1
MT8981D
Data Sheet
16
Zarlink Semiconductor Inc.
Figure 16 - Serial Inputs
Timing is over recommended temperature & power supply voltages.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
* High Impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel time taken to discharge C
L
.
Note 1:
Processor accesses are dependent on the C4i clock, and so some timings are expressed as multiples of the C4i clock period.
AC Electrical Characteristics
- Processor Bus (Figures 11 and 17)
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
Chip Select Setup Time
t
CSS
20
0
ns
2
Read/Write Setup Time
t
RWS
25
5
ns
3
Address Setup Time
t
ADS
25
5
ns
4
Acknowledgement Delay
Fast
Slow
t
AKD
40
100
ns
C
L
=150 pF
C4i cycles
1
t
AKD
2.7
7.2
cycles
5
Fast Write Data Setup Time
t
FWS
20
ns
C4i cycles
1
C4i cycles
1
, C
L
= 150 pF
R
L
=1 K
*
, C
L
=150 pF
6
Slow Write Data Delay
t
SWD
2.0
1.7
cycles
7
Read Data Setup Time
t
RDS
0.5
cycles
8
Data Hold Time
Read
Write
t
DHT
20
ns
t
DHT
20
10
ns
9
Read Data To High Impedance
t
RDZ
50
90
ns
R
L
=1 K
*
, C
L
=150 pF
10
Chip Select Hold Time
t
CSH
0
ns
11
Read/Write Hold Time
t
RWH
0
ns
12
Address Hold Time
t
ADH
0
ns
13
Acknowledgement Hold Time
t
AKH
10
60
80
ns
R
L
=1 K
*
, C
L
=150 pF
Bit Cell Boundaries
C4i
2.0V
0.8V
2.0V
0.8V
t
SIS
t
SIH
STi0
to
STi3
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