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參數(shù)資料
| 型號(hào)： | MT8941BPR1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Advanced T1/CEPT Digital Trunk PLL |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQCC28 |
| 封裝： | LEAD FREE, PLASTIC, MS-018AB, LCC-28 |
| 文件頁(yè)數(shù)： | 17/27頁(yè) |
| 文件大小： | 491K |
| 代理商： | MT8941BPR1 |
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MT8941B
Data Sheet
17
Zarlink Semiconductor Inc.
Figure 13 - Generation of the ST-BUS Timing Signals
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
Absolute Maximum Ratings*
- Voltages are with respect to ground (V
SS
) unless otherwise stated.
Parameter
Symbol
Min.
Max.
Units
1
Supply Voltage
V
DD
V
I
I
IK/OK
I
O
I
DD
/I
SS
T
ST
P
D
P
D
-0.3
7.0
V
2
Voltage on any pin
V
SS
-0.3
V
DD
+0.3
±
10
V
3
Input/Output Diode Current
mA
4
Output Source or Sink Current
±
25
mA
5
DC Supply or Ground Current
±
50
mA
6
Storage Temperature
-55
125
o
C
7
Package Power Dissipation - Plastic DIP
- PLCC
1200
600
mW
mW
Recommended Operating Conditions
- Voltages are with respect to ground (V
SS
) unless otherwise stated.
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
Supply Voltage
V
DD
V
IH
V
IL
T
A
4.5
5.0
5.5
V
2
Input HIGH Voltage
2.0
V
DD
0.8
V
3
Input LOW Voltage
V
SS
-40
V
4
Operating Temperature
25
85
o
C
Crystal Clock
(16.384 MHz)
MT8941B
MS0
MS1
MS2
MS3
F0i
C12i
EN
CV
C8Kb
C16i
EN
C4o
EN
C2o
Ai
Bi
V
SS
V
DD
C4b
RST
C4o
C2o
C2o
F0b
ST-BUS
TIMING
SIGNALS
DPLL #1 - NOT USED
DPLL #2 - NORMAL MODE
(MS0=0; MS1=0;
MS2=1; MS3=1)
V
DD
R
C
MT8941B
MS0
MS1
MS2
MS3
F0i
C12i
EN
CV
C8Kb
C16i
EN
C4o
EN
C2o
Ai
Bi
V
SS
V
DD
C4b
RST
C4o
C2o
C2o
F0b
DPLL #1 - NOT USED
DPLL #2 - FREE-RUN MODE
(MS0=1; MS1=0;MS2=1;
MS3=1)
Crystal Clock
(16.384 MHz)
V
DD
R
C
ST-BUS
TIMING
SIGNALS
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