參數(shù)資料
型號(hào)： MT8941BPR1
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Advanced T1/CEPT Digital Trunk PLL
中文描述： SPECIALTY TELECOM CIRCUIT, PQCC28
封裝： LEAD FREE, PLASTIC, MS-018AB, LCC-28
文件頁(yè)數(shù)： 10/27頁(yè)
文件大小： 491K
代理商： MT8941BPR1
MT8941B
Data Sheet
10
Zarlink Semiconductor Inc.
The T1 and CEPT standards specify that, for free running equipment, the output clock tolerance must be less than
or equal to
±
32ppm and
±
50ppm respectively. This requirement restricts the oscillators of DPLL #1 and DPLL #2
to have maximum tolerances of
±
32ppm and
±
50ppm respectively.
Table 6 - Lock-in Range vs. Oscillator Frequency Tolerance
Figure 5 - The Spectrum of the Inherent Jitter for either PLL
Oscillator Clock*
Tolerance (
±
ppm)
Lock-in Range (
±
Hz)
DPLL #1
2.55
2.51
2.43
2.33
2.19
1.79
1.39
1.19
DPLL #2
1.91
1.87
1.79
1.69
1.55
1.15
.75
.55
5
10
20
32
50
100
150
175
Note: * Please refer to the section on “Jitter Performance and Lock-in
Range” for recommended oscillator tolerances for DPLL #1 & #2.
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