參數(shù)資料
型號(hào): MT8941BP1
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Advanced T1/CEPT Digital Trunk PLL
中文描述: SPECIALTY TELECOM CIRCUIT, PQCC28
封裝: LEAD FREE, PLASTIC, MS-018AB, LCC-28
文件頁數(shù): 11/27頁
文件大小: 491K
代理商: MT8941BP1
MT8941B
Data Sheet
11
Zarlink Semiconductor Inc.
Figure 6 - The Jitter Transfer Function for PLL1
Figure 7 - The Jitter Transfer Function for PLL2
However, if DPLL #1 and DPLL #2 are daisy-chained as shown in Figures 9 and 10, the output clock tolerance of
DPLL #1 will be equal to that of the DPLL #2 oscillator when DPLL #2 is free-running. In this case, the oscillator
tolerance of DPLL #1 has no impact on its output clock tolerance. For this reason, it is recommended to use a
±
32 ppm oscillator for DPLL #2 and a
±
100 ppm oscillator for DPLL #1.
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