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MT8941B
Data Sheet
6
Zarlink Semiconductor Inc.
Table 1 - Major Modes of DPLL #1
Table 2 - Major Modes of DPLL #2
M
S
0
M
S
1
Mode of
Operation
Function
X
0
NORMAL
Provides the T1 (1.544 MHz) clock synchronized
to the falling edge of the input frame pulse (F0i).
0
1
DIVIDE-1
DPLL #1 divides the CVb input by 193. The
divided output is connected to DPLL #2.
1
1
DIVIDE-2
DPLL #1 divides the CVb input by 256. The
divided output is connected to DPLL #2.
Note: X: indicates don’t care
M
S
0
M
S
1
Mode of
Operation
Function
0
0
NORMAL
Provides CEPT/ST-BUS timing signals locked
to the falling edge of the 8 kHz input signal at
C8Kb.
1
0
FREE-RUN
Provides CEPT/ST-BUS timing and framing
signals with no external inputs, except the
master clock.
0
1
SINGLE
CLOCK-1
Provides CEPT/ST-BUS timing signals locked
to the falling edge of the 8 kHz internal signal
provided by DPLL #1.
1
1
SINGLE
CLOCK-2
Provides CEPT/ST-BUS timing signals locked
to the falling edge of the 8 kHz internal signal
provided by DPLL #1.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT8941AP | CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
| MT8966 | Integrated PCM Filter Codec |
| MT8966 | Integrated PCM Filter Codec |
| MT8966AS | Integrated PCM Filter Codec |
| MT8981DP1 | ISO-CMOS ST-BUS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8941AP | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
| MT8941B | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
| MT8941BE | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Advanced T1/CEPT Digital Trunk PLL |
| MT8941BP | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Advanced T1/CEPT Digital Trunk PLL |
| MT8941BP1 | 制造商:Microsemi Corporation 功能描述:ADVANCED T1/CEPT DIG TRUNK PLL EOL160209 |
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