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參數(shù)資料
| 型號： | MT8931C |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | CMOS ST-BUS⑩ FAMILY Subscriber Network Interface Circuit Preliminary Information |
| 中文描述： | 意法半導體的CMOS總線⑩家庭用戶網(wǎng)絡接口電路的初步信息 |
| 文件頁數(shù)： | 7/39頁 |
| 文件大?。?/td> | 833K |
| 代理商： | MT8931C |
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Data Sheet
MT8931C
7
Framing
The valid frame structure transmitted by the NT and
TE contains the following (refer Fig. 6):
NT to TE:
- Framing bit (F)
- B1 and B2 channels (B1,B2)
- DC balancing bits (L)
- D-channel bits (D0, D1)
- Auxiliary framing and N bit (Fa, N), N=Fa
- Activation bit (A)
- D-echo channel bits (E)
- Multiframing bit (M)
- S-channel bit
TE to NT:
- Framing bit (F)
- B1 and B2 channels (B1, B2)
- DC balancing bits (L)
- D-channel bits (D0, D1)
- Auxiliary framing bit (Fa) or Q-channel bit
The framing mechanism on the S-interface makes
use of line code violations to identify frame
boundaries. The F-bit violates the alternating line
code sequence to allow for quick identification of the
frame boundaries. To secure the frame alignment,
the next mark following the frame balancing bit
(L) will also produce a line code violation. If the
data following the balancing bit is all binary ones,
the zero in the auxiliary framing bit (Fa) or N-bit (for
the direction NT to TE) will provide successive
violations to ensure that the 14 bit criterion (13 bit
criterion in the direction TE to NT) specified in
Recommendations I.430 and T1.605 is satisfied. If
the B1-channel is not all binary ones, the first zero
following the L-bit will violate the line code sequence,
thus allowing subsequent marks to alternate without
bipolar violations.
The Fa and N bits can also be used to identify a
multiframe structure (when this is done, the 14 bit
criterion may not be met). This multiframe structure
will make provisions for a low speed signalling
channel to be used in the TE to NT direction
(Q-channel). It will consist of a five frame multiframe
which can be identified by the binary inversion of the
Fa and N-bit on the first frame and consequently on
every fifth frame of the multiframe. Upon detection
of the multiframe signal, the TE will replace the next
Fa-bit to be transmitted with the Q-bit.
The DC balancing bits (L) are used to remove any
DC content from the line. The balancing bit will be a
mark if the number of preceding marks up to the
previous balancing bit is odd. If the number of marks
is even, the L-bit will be a space.
The A-bit is used by the NT during line activation
procedures (refer to state activation diagrams). The
state of the A-bit will advise the TE if the NT has
achieved synchronization.
The E-bit is the D-echo channel. The NT will reflect
the binary value of the received D-channel into the
E-bits. This is used to establish the access
contention
resolution
in
configuration. This is described in more detail in the
section of the D-channel priority mechanism.
a
point-to-multipoint
The M-bit is a second level of multiframing which is
used for structuring the Q-bits. The frame with M-
bit=1 identifies frame #1 in the twenty frame
multiframe. The Q-channel is then received as
shown in Table 1. All synchronization with the
multiframes must be performed externally.
Table 1. Q-channel Allocation
Bit Order
When using the B-channels for PCM voice, the first
bit to be transmitted on the S-Bus should be the sign
bit. This complies with the existing telecom
standards which transmit PCM voice as most
significant bit first. However, if the B-channels are to
carry data, the bit ordering must be reversed to
comply with the existing datacom standards (i.e.,
least significant bit first).
These contradicting standards place a restriction on
all information input and output through the serial
and parallel ports. Information transferred through
the serial ports, will maintain the integrity of the bit
order. Data sent to either serial port from the parallel
port, will transmit the least significant bit first.
Therefore,
a
PCM
byte
microprocessor port must be reordered to have the
sign bit as the least significant bit.
input
through
the
When the microprocessor reads D, B1 or B2 channel
data of either ST-BUS or S-bus serial port, the least
significant bit read is the first bit received on that
particular channel of either serial port.
The D-channel received on the serial ST-BUS ports
must be ordered with the least significant bit first as
shown in Figure 4. This also applies to the
D-channel directed to the ST-BUS from the
microprocessor port.
FRAME #
1
6
11
16
Q-BIT
Q1
Q2
Q3
Q4
M-BIT
1
0
0
0
相關PDF資料 |
PDF描述 |
|---|---|
| MT8931CC | CMOS ST-BUS⑩ FAMILY Subscriber Network Interface Circuit Preliminary Information |
| MT8931CP | CMOS ST-BUS⑩ FAMILY Subscriber Network Interface Circuit |
| MT8941 | Advanced T1/CEPT Digital Trunk PLL |
| MT8941BE | Advanced T1/CEPT Digital Trunk PLL |
| MT8941BP | Advanced T1/CEPT Digital Trunk PLL |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT8931C-1 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Subscriber Network Interface Circuit |
| MT8931CC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Subscriber Network Interface Circuit Preliminary Information |
| MT8931CE | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Subscriber Network Interface Circuit |
| MT8931CP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Subscriber Network Interface Circuit |
| MT8940 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY T1/CEPT Digital Trunk PLL |
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