參數(shù)資料
型號(hào): MT88L89
廠商: Mitel Networks Corporation
英文描述: 3V Integrated DTMF Transceiver with Adaptive Micro Interface(3V 集成雙音多頻信號(hào)(DTMF)接收器(帶自適應(yīng)微接口))
中文描述: 3V的雙音多頻收發(fā)器集成自適應(yīng)微型接口(3V的集成雙音多頻信號(hào)(DTMF)的接收器(帶自適應(yīng)微接口))
文件頁(yè)數(shù): 4/28頁(yè)
文件大?。?/td> 210K
代理商: MT88L89
MT88L89
4-126
Figure 3 - Single-Ended Input Configuration
Figure 4 - Differential Input Configuration
0= LOGIC LOW, 1= LOGIC HIGH
Table 1 - Functional Encode/Decode Table
Following the filter section is a decoder employing
digital counting techniques to determine the
frequencies of the incoming tones and to verify that
they correspond to standard DTMF frequencies. A
complex averaging algorithm protects against tone
simulation by extraneous signals such as voice while
providing tolerance to small frequency deviations
and variations. This averaging algorithm has been
developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of
interfering frequencies (third tones) and noise. When
the detector recognizes the presence of two valid
tones (this is referred to as the “signal condition” in
some industry specifications) the “Early Steering”
(ESt) output will go to an active state. Any
subsequent loss of signal condition will cause ESt to
assume an inactive state.
Steering Circuit
Before registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred to
as character recognition condition). This check is
performed by an external RC time constant driven by
ESt. A logic high on ESt causes v
c
(see Figure 5) to
rise as the capacitor discharges. Provided that the
signal condition is maintained (ESt remains high) for
the validation period (t
GTP
), v
c
reaches the threshold
(V
TSt
) of the steering logic to register the tone pair,
latching its corresponding 4-bit code (see Table 1)
into the Receive Data Register. At this point the GT
output is activated and drives v
c
to V
DD
. GT
continues to drive high as long as ESt remains high.
Finally, after a short delay to allow the output latch to
settle, the delayed steering output flag goes high,
signalling that a received tone pair has been
registered. The status of the delayed steering flag
can be monitored by checking the appropriate bit in
the status register. If Interrupt mode has been
selected, the IRQ/CP pin will pull low when the
delayed steering flag is active.
The contents of the output latch are updated on an
active delayed steering transition. This data is
presented to the four bit bidirectional data bus when
the Receive Data Register is read. The steering
circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting
signals too short to be considered valid, the receiver
will tolerate signal interruptions (drop out) too short
to be considered a valid pause. This facility, together
with the capability of selecting the steering time
constants externally, allows the designer to tailor
performance to meet a wide variety of system
requirements.
F
LOW
F
HIGH
DIGIT
D
3
D
2
D
1
D
0
697
1209
1
0
0
0
1
697
1336
2
0
0
1
0
697
1477
3
0
0
1
1
770
1209
4
0
1
0
0
770
1336
5
0
1
0
1
770
1477
6
0
1
1
0
852
1209
7
0
1
1
1
852
1336
8
1
0
0
0
852
1477
9
1
0
0
1
941
1336
0
1
0
1
0
941
1209
*
1
0
1
1
941
1477
#
1
1
0
0
697
1633
A
1
1
0
1
770
1633
B
1
1
1
0
852
1633
C
1
1
1
1
941
1633
D
0
0
0
0
C
R
IN
R
F
IN+
IN-
GS
V
Ref
VOLTAGE GAIN
(A
V
) = R
F
/ R
IN
MT88L89
C1
C2
R1
R2
R3
R4
R5
IN+
IN-
GS
V
Ref
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2
R1 = R4
R3 = (R2R5)/(R2 + R5)
VOLTAGE GAIN
(A
V
diff) = R5/R1
INPUT IMPEDANCE
(Z
IN
diff) = 2
R1
2
+ (1/
ω
C)
2
MT88L89
FOR UNITY GAIN
R5=R1
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