參數(shù)資料
型號: MT88L89
廠商: Mitel Networks Corporation
英文描述: 3V Integrated DTMF Transceiver with Adaptive Micro Interface(3V 集成雙音多頻信號(DTMF)接收器(帶自適應(yīng)微接口))
中文描述: 3V的雙音多頻收發(fā)器集成自適應(yīng)微型接口(3V的集成雙音多頻信號(DTMF)的接收器(帶自適應(yīng)微接口))
文件頁數(shù): 2/28頁
文件大小: 210K
代理商: MT88L89
MT88L89
4-124
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
20
24
28
1
2
3
1
2
3
1
2
4
IN+
IN-
GS
Non-inverting
op-amp input.
Inverting
op-amp input.
Gain Select
. Gives access to output of front end differential amplifier for connection of
feedback resistor.
Reference Voltage
output (V
DD
/2).
Ground (0V).
Oscillator
input. This pin can also be driven directly by an external clock. CMOS
compatible.
Oscillator
output. A 3.579545 MHz crystal connected between OSC1 and OSC2
completes the internal oscillator circuit. Leave open circuit when OSC1 is driven
externally.
Output from internal DTMF transmitter. High impedance when TOUT bit in Control
Register A (CRA) is set to low. Requires resistive termination to V
SS
.
(Motorola)
Read/Write
or (Intel)
Write
microprocessor input. CMOS compatible.
4
5
6
4
5
6
6
7
8
V
Ref
V
SS
OSC1
7
7
9
OSC2
8
10
12
TONE
9
11
13
R/W
(
WR
)
CS
10
12
14
Chip Select
input must be gated externally by either address strobe (AS), valid memory
address (VMA) or address latch enable (ALE) signal, depending on processor used.
See Figure 12. Must not be tied low. CMOS compatible.
Register Select
input. Refer to Table 3 for bit interpretation. CMOS compatible.
DS
(
RD) (Motorola)
Data Strobe
or (Intel)
Read
microprocessor input. Activity on this input is
only required when the device is being accessed. CMOS compatible.
IRQ/CP
Interrupt Request/Call Progress
(open drain) output. In interrupt mode, this output
goes low when a valid DTMF tone burst has been transmitted or received. In call
progress mode, this pin will output a rectangular signal representative of the input signal
applied at the input op-amp. The input signal must be within the bandwidth limits of the
call progress filter. See Figure 10.
D0-D3
Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or RD = 1
(Intel). CMOS compatible.
ESt
Early Steering
output. Presents a logic high once the digital algorithm has detected a
valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt
to return to a logic low.
11
12
13
14
15
17
RS0
13
15
18
14-
17
18
18-
21
22
19-
22
26
1
2
3
4
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
TONE
R/W/WR
CS
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
DS/RD
RS0
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
TONE
R/W/WR
CS
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ/CP
DS/RD
RS0
24 PIN SSOP
20 PIN /PLASTIC DIP/SOIC
28 PIN PLCC
4
5
6
7
8
9
10
11
25
24
23
22
21
20
19
G
NC
VRef
VSS
OSC1
OSC2
NC
NC
D
3
2
1
2
2
2
1
1
1
1
1
1
1
N
I
I
V
S
E
T
R
C
R
N
I
NC
NC
NC
D3
D2
D1
D0
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