參數(shù)資料
型號: MT88E46
廠商: Mitel Networks Corporation
英文描述: Bellcore Compliant Calling Number Identification Circuit(兼容貝爾內核主叫識別電路)
中文描述: 貝爾通訊兼容主叫號碼識別電路(兼容貝爾內核主叫識別電路)
文件頁數(shù): 17/25頁
文件大小: 111K
代理商: MT88E46
17
Advance Information
MT88E46
AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated.
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
*Notes:
1. OSC1 at 3.579545 MHz
±
0.1%.
2. FSK input data at 1200
±
12 baud.
3. Function of signal condition.
AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
AC Electrical Characteristics
- Mode 0 FSK Data Interface Timing
Characteristics
Sym
Min
Typ
Max
Units
Notes*
1
DR
Rise time
t
RR
-
-
200
ns
into 50pF load
See Figure 11
2
Fall time
t
RF
-
-
200
ns
into 50pF load
See Figure 11
3
Low time
t
RL
415
416
417
μ
s
1.
See Figs. 11, 14, 15
4
DATA
Rate
1188
1200
1212
baud
2
5
Input FSK to DATA delay
t
IDD
-
1
5
ms
See Figure 14
6
DATA
DCLK
Rise time
t
R
-
-
200
ns
into 50pF load
See Figure 10
7
Fall time
t
F
-
-
200
ns
into 50pF load
See Figure 10
8
DATA to DCLK delay
t
DCD
6
416
-
μ
s
1, 2, 3
See Figure 10
9
DCLK to DATA delay
t
CDD
6
416
-
μ
s
1, 2, 3
See Figure 10
10
DCLK
Frequency
f
DCLK0
t
CH
t
CL
1201.6
1202.8
1204
Hz
1. See Figure 14
11
High time
415
416
417
μ
s
μ
s
1. See Figures 10, 14
12
Low time
415
416
417
1. See Figures 10, 14
13
DCLK
DR
DCLK to DR delay
t
CRD
415
416
417
μ
s
1. See Figure 14
AC Electrical Characteristics
- Mode 1 FSK Data Interface Timing
Characteristics
Sym
Min
Max
Units
Notes
1
DCLK
Frequency
f
DCLK1
-
1
MHz
See Figure 15
2
Duty cycle
30
70
%
3
Rise time
t
R1
t
DDS
t
DDH
-
100
ns
See Figure 12
4
DCLK
DR
DCLK low set up to DR
500
-
ns
See Figure 15
5
DCLK low hold time after DR
500
-
ns
See Figure 15
AC Electrical Characteristics
- General Timing
Characteristics
Sym
Min
Max
Units
Notes
1
OSC2
Power-up time
t
PU
t
PD
-
50
ms
See Figures 16, 17
2
Power-down time
-
10
ms
See Figure 16
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