參數(shù)資料
型號: MT8889CS-1
廠商: Mitel Networks Corporation
英文描述: Integrated DTMFTransceiver with Adaptive Micro Interface
中文描述: 綜合DTMFTransceiver自適應(yīng)微型接口
文件頁數(shù): 9/18頁
文件大?。?/td> 356K
代理商: MT8889CS-1
MT8889C/MT8889C-1
4-115
The adaptive micro interface provides access to five
internal registers. The read-only Receive Data
Register contains the decoded output of the last
valid DTMF digit received. Data entered into the
write-only Transmit Data Register will determine
which tone pair is to be generated (see Table 1 for
coding details). Transceiver control is accomplished
with two control registers (see Tables 6 and 7), CRA
and CRB, which have the same address. A write
operation to CRB is executed by first setting the
most significant bit (b3) in CRA. The following write
operation to the same address will then be directed
to CRB, and subsequent write cycles will be directed
back to CRA. The read-only status register indicates
the current transceiver state (see Table 8).
A software reset must be included at the beginning
of all programs to initialize the control registers upon
power-up or power reset (see Figure 15). Refer to
Tables 4-7 for bit descriptions of the two control
registers.
The multiplexed IRQ/CP pin can be programmed to
generate an interrupt upon validation of DTMF
signals or when the transmitter is ready for more
data (burst mode only). Alternatively, this pin can be
configured to provide a square-wave output of the
call progress signal. The IRQ/CP pin is an open drain
output and requires an external pull-up resistor (see
Figure 13).
Table 3. Internal Register Functions
Table 4. CRA Bit Positions
Table 5. CRB Bit Positions
Motorola
Intel
RS0
R/W
WR
RD
FUNCTION
0
0
0
1
Write to Transmit
Data Register
0
1
1
0
Read from Receive
Data Register
1
0
0
1
Write to Control Register
1
1
1
0
Read from Status Register
b3
b2
b1
b0
RSEL
IRQ
CP/DTMF
TOUT
b3
b2
b1
b0
C/R
S/D
TEST
BURST
ENABLE
Figure 12 a) & b) - MT8889 Interface Connections for Various Intel and Motorola Micros
MC6800/6802
MT8889/MT8889C-1
MT8889C/MT8889C-1
A0-A15
VMA
D0-D3
RW
Φ
2
MC68HC11
MC6809
MT8889/MT8889C-1
MT8889C/MT8889C-1
8031/8051
8080/8085
CS
RS0
D0-D3
R/W/WR
DS/RD
A8-A15
AS
AD0-AD3
RW
CS
RS0
DS/RD
D0-D3
R/W/WR
DS
A0-A15
Q
E
D0-D3
R/W
CS
RS0
D0-D3
R/W/WR
DS/RD
A8-A15
ALE
P0
RD
WR
CS
D0-D3
RS0
DS/RD
R/W/WR
(a)
(b)
相關(guān)PDF資料
PDF描述
MT8889C Integrated DTMFTransceiver with Adaptive Micro Interface
MT8889CC Integrated DTMFTransceiver with Adaptive Micro Interface
MT8889CE Integrated DTMFTransceiver with Adaptive Micro Interface
MT8889CN Integrated DTMFTransceiver with Adaptive Micro Interface
MT8889CS Integrated DTMFTransceiver with Adaptive Micro Interface
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