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參數(shù)資料
| 型號(hào)： | MT8889CS-1 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Integrated DTMFTransceiver with Adaptive Micro Interface |
| 中文描述： | 綜合DTMFTransceiver自適應(yīng)微型接口 |
| 文件頁數(shù)： | 16/18頁 |
| 文件大小： | 356K |
| 代理商： | MT8889CS-1 |
MT8889C/MT8889C-1
4-122
Characteristics are over recommended operating conditions unless otherwise stated
Typical figures are at 25°C, V
DD
=5V, and for design aid only: not guaranteed and not subject to production testing
NOTES: 1)
dBm=decibels above or below a reference power of 1 mW into a 600 ohm load.
2)
Digit sequence consists of all 16 DTMF tones.
3)
Tone duration=40 ms. Tone pause=40 ms.
4)
Nominal DTMF frequencies are used.
5)
Both tones in the composite signal have an equal amplitude.
6)
The tone pair is deviated by ± 1.5 %±2 Hz.
7)
Bandwidth limited (3 kHz) Gaussian noise.
8)
The precise dial tone frequencies are 350 and 440 Hz (±2 %).
9)
Guaranteed by design and characterization. Not subject to production testing.
10)
Referenced to the lowest amplitude tone in the DTMF signal.
11)
For guard time calculation purposes.
Figure 16 - DS/RD/WR Clock Pulse
AC Electrical Characteristics
- MPU Interface
- Voltages are with respect to ground (V
SS
), unless otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
Conditions
1
DS/RD/WR clock frequency
f
CYC
t
CYC
4.0
MHz
Figure 16
2
DS/RD/WR cycle period
250
ns
Figure 16
3
DS/RD/WR low pulse width
t
CL
t
CH
t
R,
t
F
t
RWS
t
RWH
t
AS
t
AH
t
DHR
t
DDR
t
DSW
t
DHW
t
CSS
t
CSH
C
IN
C
OUT
150
ns
Figure 16
4
DS/RD/WR high pulse width
100
ns
Figure 16
5
DS/RD/WR rise and fall time
20
ns
Figure 16
6
R/W setup time
23
ns
Figures 17 & 18
7
R/W hold time
20
ns
Figures 17 & 18
8
Address setup time (RS0)
0
ns
Figures 17 - 20
9
Address hold time (RS0)
40
20
ns
Figures 17 - 20
10
Data hold time (read)
22
ns
Figures 17 - 20
11
DS/RD to valid data delay (read)
100
ns
Figures 17 - 20
12
Data setup time (write)
45
ns
Figures 17 - 20
13
Data hold time (write)
10
ns
Figures 17 - 20
14
Chip select setup time
45
35
ns
Figures 17 - 20
15
Chip select hold time
40
ns
Figures 17 - 20
16
Input Capacitance (data bus)
5
pF
17
Output Capacitance (IRQ/CP)
5
pF
t
CYC
t
R
t
CH
t
CL
DS/RD/WR
t
F
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